Searched refs:CK_TOP_CB_M_D4 (Results 1 – 5 of 5) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7981.c | 53 PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
141 CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
145 CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
152 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
158 CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
162 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
165 CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
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| A D | clk-mt7986.c | 51 PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
119 CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2,
124 CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, CK_TOP_WEDMCU_D5_D2,
131 CK_TOP_CB_M_D4, CK_TOP_WEDMCU_D5_D2 };
137 CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 };
140 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt7986-clk.h | 57 #define CK_TOP_CB_M_D4 3 macro
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| A D | mt7981-clk.h | 59 #define CK_TOP_CB_M_D4 5 macro
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| /u-boot/arch/arm/dts/ |
| A D | mt7986.dtsi | 165 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>,
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