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Searched refs:CK_TOP_CB_NET2_D4 (Results 1 – 4 of 4) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7986-clk.h76 #define CK_TOP_CB_NET2_D4 22 macro
A Dmt7981-clk.h83 #define CK_TOP_CB_NET2_D4 29 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7981.c79 PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
169 CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, CK_TOP_CB_NET2_D4,
208 static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D4 };
A Dclk-mt7986.c72 PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
156 CK_TOP_CB_NET2_D4 };

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