Searched refs:CK_TOP_NET1_D5_D2 (Results 1 – 5 of 5) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt7986-clk.h | 71 #define CK_TOP_NET1_D5_D2 17 macro
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| A D | mt7981-clk.h | 76 #define CK_TOP_NET1_D5_D2 22 macro
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7986.c | 66 PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
147 CK_TOP_NET1_D5_D2 };
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| A D | clk-mt7981.c | 71 PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
212 CK_TOP_NET1_D5_D2 };
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| /u-boot/arch/arm/dts/ |
| A D | mt7986.dtsi | 290 <&topckgen CK_TOP_NET1_D5_D2>;
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