Searched refs:CK_TOP_NET1_D5_D4 (Results 1 – 4 of 4) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7986.c | 67 PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
123 CK_TOP_CB_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
130 CK_TOP_NET2_D3_D2, CK_TOP_NET1_D5_D4,
137 CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 };
139 static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
143 CK_TOP_NET1_D5_D4, CK_TOP_NET2_D4_D2,
199 static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
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| A D | clk-mt7981.c | 72 PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
145 CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
151 CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
158 CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
161 static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
165 CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
226 static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt7986-clk.h | 72 #define CK_TOP_NET1_D5_D4 18 macro
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| A D | mt7981-clk.h | 77 #define CK_TOP_NET1_D5_D4 23 macro
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