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Searched refs:CK_TOP_PWM_SEL (Results 1 – 6 of 6) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7986-clk.h114 #define CK_TOP_PWM_SEL 60 macro
A Dmt7981-clk.h135 #define CK_TOP_PWM_SEL 81 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7981.c102 TOP_FACTOR(CK_TOP_PWM_BCK, "pwm_bck", CK_TOP_PWM_SEL, 1, 1),
255 TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3,
320 TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
A Dclk-mt7986.c230 TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8,
311 TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
/u-boot/arch/arm/dts/
A Dmt7981.dtsi149 assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
A Dmt7986.dtsi161 assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,

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