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Searched refs:CLKID_FCLK_DIV2 (Results 1 – 10 of 10) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Daxg-clkc.h13 #define CLKID_FCLK_DIV2 2 macro
A Dg12a-clkc.h13 #define CLKID_FCLK_DIV2 2 macro
A Dgxbb-clkc.h12 #define CLKID_FCLK_DIV2 4 macro
/u-boot/arch/arm/dts/
A Dmeson-gxbb.dtsi296 <&clkc CLKID_FCLK_DIV2>,
298 <&clkc CLKID_FCLK_DIV2>;
779 <&clkc CLKID_FCLK_DIV2>;
787 <&clkc CLKID_FCLK_DIV2>;
795 <&clkc CLKID_FCLK_DIV2>;
A Dmeson-gxl.dtsi133 <&clkc CLKID_FCLK_DIV2>,
135 <&clkc CLKID_FCLK_DIV2>;
848 <&clkc CLKID_FCLK_DIV2>;
856 <&clkc CLKID_FCLK_DIV2>;
864 <&clkc CLKID_FCLK_DIV2>;
A Dmeson-g12-common.dtsi177 <&clkc CLKID_FCLK_DIV2>,
179 <&clkc CLKID_FCLK_DIV2>;
2331 <&clkc CLKID_FCLK_DIV2>;
2343 <&clkc CLKID_FCLK_DIV2>;
2355 <&clkc CLKID_FCLK_DIV2>;
A Dmeson-axg.dtsi276 <&clkc CLKID_FCLK_DIV2>,
278 <&clkc CLKID_FCLK_DIV2>;
1892 <&clkc CLKID_FCLK_DIV2>;
1904 <&clkc CLKID_FCLK_DIV2>;
/u-boot/drivers/clk/meson/
A Dg12a.c131 MESON_GATE(CLKID_FCLK_DIV2, HHI_FIX_PLL_CNTL1, 24),
789 case CLKID_FCLK_DIV2: in meson_clk_get_rate_by_id()
907 case CLKID_FCLK_DIV2: in meson_clk_set_rate_by_id()
A Daxg.c247 case CLKID_FCLK_DIV2: in meson_clk_get_rate_by_id()
A Dgxbb.c735 case CLKID_FCLK_DIV2: in meson_clk_get_rate_by_id()
820 case CLKID_FCLK_DIV2: in meson_clk_set_rate_by_id()

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