Searched refs:CLKID_FCLK_DIV3 (Results 1 – 12 of 12) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | axg-clkc.h | 14 #define CLKID_FCLK_DIV3 3 macro
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| A D | g12a-clkc.h | 14 #define CLKID_FCLK_DIV3 3 macro
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| A D | gxbb-clkc.h | 13 #define CLKID_FCLK_DIV3 5 macro
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| /u-boot/drivers/clk/meson/ |
| A D | g12a.c | 132 MESON_GATE(CLKID_FCLK_DIV3, HHI_FIX_PLL_CNTL1, 20),
393 CLKID_FCLK_DIV3,
422 CLKID_FCLK_DIV3,
434 CLKID_FCLK_DIV3,
582 CLKID_FCLK_DIV3, in meson_clk81_get_rate()
792 case CLKID_FCLK_DIV3: in meson_clk_get_rate_by_id()
908 case CLKID_FCLK_DIV3: in meson_clk_set_rate_by_id()
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| A D | gxbb.c | 177 MESON_GATE(CLKID_FCLK_DIV3, HHI_MPLL_CNTL6, 28),
418 CLKID_FCLK_DIV3,
442 CLKID_FCLK_DIV3,
582 CLKID_FCLK_DIV3, in meson_clk81_get_rate()
738 case CLKID_FCLK_DIV3: in meson_clk_get_rate_by_id()
821 case CLKID_FCLK_DIV3: in meson_clk_set_rate_by_id()
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| A D | axg.c | 95 CLKID_FCLK_DIV3, in meson_clk81_get_rate()
250 case CLKID_FCLK_DIV3: in meson_clk_get_rate_by_id()
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| /u-boot/arch/arm/dts/ |
| A D | meson-g12.dtsi | 83 <&clkc CLKID_FCLK_DIV3>,
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| A D | meson-sm1.dtsi | 162 <&clkc CLKID_FCLK_DIV3>,
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| A D | meson-gxbb.dtsi | 753 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
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| A D | meson-gxl.dtsi | 822 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
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| A D | meson-axg.dtsi | 1312 <&clkc CLKID_FCLK_DIV3>,
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| A D | meson-g12-common.dtsi | 1647 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
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