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Searched refs:CLKID_FCLK_DIV4 (Results 1 – 20 of 20) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Daxg-clkc.h15 #define CLKID_FCLK_DIV4 4 macro
A Dg12a-clkc.h15 #define CLKID_FCLK_DIV4 4 macro
A Dgxbb-clkc.h14 #define CLKID_FCLK_DIV4 6 macro
/u-boot/drivers/clk/meson/
A Dg12a.c133 MESON_GATE(CLKID_FCLK_DIV4, HHI_FIX_PLL_CNTL1, 21),
394 CLKID_FCLK_DIV4,
421 CLKID_FCLK_DIV4,
433 CLKID_FCLK_DIV4,
581 CLKID_FCLK_DIV4, in meson_clk81_get_rate()
795 case CLKID_FCLK_DIV4: in meson_clk_get_rate_by_id()
909 case CLKID_FCLK_DIV4: in meson_clk_set_rate_by_id()
A Dgxbb.c178 MESON_GATE(CLKID_FCLK_DIV4, HHI_MPLL_CNTL6, 29),
417 CLKID_FCLK_DIV4,
441 CLKID_FCLK_DIV4,
581 CLKID_FCLK_DIV4, in meson_clk81_get_rate()
741 case CLKID_FCLK_DIV4: in meson_clk_get_rate_by_id()
822 case CLKID_FCLK_DIV4: in meson_clk_set_rate_by_id()
A Daxg.c94 CLKID_FCLK_DIV4, in meson_clk81_get_rate()
253 case CLKID_FCLK_DIV4: in meson_clk_get_rate_by_id()
/u-boot/arch/arm/dts/
A Dmeson-gx-libretech-pc.dtsi345 clocks = <&clkc CLKID_FCLK_DIV4>;
353 clocks = <&clkc CLKID_FCLK_DIV4>;
361 clocks = <&clkc CLKID_FCLK_DIV4>;
A Dmeson-gxm-khadas-vim2.dts289 clocks = <&clkc CLKID_FCLK_DIV4>;
297 clocks = <&clkc CLKID_FCLK_DIV4>;
A Dmeson-gxl-s905x-p212.dtsi172 clocks = <&clkc CLKID_FCLK_DIV4>;
A Dmeson-gxbb-p20x.dtsi153 clocks = <&clkc CLKID_FCLK_DIV4>;
A Dmeson-gxl-s905w-jethome-jethub-j80.dts119 clocks = <&clkc CLKID_FCLK_DIV4>;
A Dmeson-gxbb-wetek.dtsi188 clocks = <&clkc CLKID_FCLK_DIV4>;
A Dmeson-gx-p23x-q20x.dtsi242 clocks = <&clkc CLKID_FCLK_DIV4>;
A Dmeson-gxbb-nanopi-k2.dts298 clocks = <&clkc CLKID_FCLK_DIV4>;
A Dmeson-g12.dtsi84 <&clkc CLKID_FCLK_DIV4>,
A Dmeson-axg.dtsi1250 assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
1253 <&clkc CLKID_FCLK_DIV4>,
1313 <&clkc CLKID_FCLK_DIV4>,
A Dmeson-sm1.dtsi163 <&clkc CLKID_FCLK_DIV4>,
A Dmeson-gxbb.dtsi756 <&clkc CLKID_FCLK_DIV4>,
A Dmeson-gxl.dtsi825 <&clkc CLKID_FCLK_DIV4>,
A Dmeson-g12-common.dtsi1650 <&clkc CLKID_FCLK_DIV4>,

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