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Searched refs:CLK_BUS_I2C2 (Results 1 – 25 of 27) sorted by relevance

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/u-boot/include/dt-bindings/clock/
A Dsuniv-ccu-f1c100s.h34 #define CLK_BUS_I2C2 36 macro
A Dsun8i-a23-a33-ccu.h80 #define CLK_BUS_I2C2 53 macro
A Dsun8i-a83t-ccu.h89 #define CLK_BUS_I2C2 52 macro
A Dsun50i-a64-ccu.h87 #define CLK_BUS_I2C2 65 macro
A Dsun50i-h616-ccu.h60 #define CLK_BUS_I2C2 74 macro
A Dsun8i-h3-ccu.h93 #define CLK_BUS_I2C2 61 macro
A Dsun9i-a80-ccu.h152 #define CLK_BUS_I2C2 121 macro
A Dsun50i-h6-ccu.h62 #define CLK_BUS_I2C2 76 macro
A Dsun8i-r40-ccu.h112 #define CLK_BUS_I2C2 89 macro
/u-boot/drivers/clk/sunxi/
A Dclk_f1c100s.c23 [CLK_BUS_I2C2] = GATE(0x068, BIT(18)),
A Dclk_a23.c31 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
A Dclk_a80.c38 [CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
A Dclk_a64.c42 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
A Dclk_a83t.c39 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
A Dclk_h6.c38 [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
A Dclk_h3.c45 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
A Dclk_h616.c40 [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
A Dclk_r40.c49 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
/u-boot/arch/arm/dts/
A Dsuniv-f1c100s.dtsi247 clocks = <&ccu CLK_BUS_I2C2>;
A Dsun50i-h616.dtsi428 clocks = <&ccu CLK_BUS_I2C2>;
A Dsun8i-a23-a33.dtsi577 clocks = <&ccu CLK_BUS_I2C2>;
A Dsunxi-h3-h5.dtsi785 clocks = <&ccu CLK_BUS_I2C2>;
A Dsun50i-h6.dtsi577 clocks = <&ccu CLK_BUS_I2C2>;
A Dsun8i-a83t.dtsi1017 clocks = <&ccu CLK_BUS_I2C2>;
A Dsun9i-a80.dtsi1136 clocks = <&ccu CLK_BUS_I2C2>;

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