CLK_DDR_BUS_OFFSET (reference) in projects: u-boot

Searched refs:CLK_DDR_BUS_OFFSET (Results 1 – 1 of 1) sorted by relevance

/u-boot/drivers/clk/starfive/
A D	clk-jh7110-pll.c	`27 #define CLK_DDR_BUS_OFFSET 0xAC macro 177 reg = readl((ulong )((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET)); in jh7110_pll_set_rate() 180 writel(reg, (ulong )((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET)); in jh7110_pll_set_rate() 193 reg = readl((ulong )((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET)); in jh7110_pll_set_rate() 196 writel(reg, (ulong )((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET)); in jh7110_pll_set_rate()`

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