CLK_DDR_BUS_PLL1_DIV2 (reference) in projects: u-boot

Searched refs:CLK_DDR_BUS_PLL1_DIV2 (Results 1 – 1 of 1) sorted by relevance

/u-boot/drivers/clk/starfive/
A D	clk-jh7110-pll.c	`29 #define CLK_DDR_BUS_PLL1_DIV2 1 macro 195 reg \|= CLK_DDR_BUS_PLL1_DIV2 << __ffs(CLK_DDR_BUS_MASK); in jh7110_pll_set_rate()`

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