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Searched refs:CLK_PLL_PERIPH0 (Results 1 – 14 of 14) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dsun50i-a64-ccu.h47 #define CLK_PLL_PERIPH0 11 macro
A Dsun50i-h616-ccu.h9 #define CLK_PLL_PERIPH0 4 macro
A Dsun8i-h3-ccu.h48 #define CLK_PLL_PERIPH0 9 macro
A Dsun9i-a80-ccu.h47 #define CLK_PLL_PERIPH0 3 macro
A Dsun50i-h6-ccu.h9 #define CLK_PLL_PERIPH0 3 macro
/u-boot/drivers/clk/sunxi/
A Dclk_a64.c17 [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)),
A Dclk_h6.c17 [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31)),
A Dclk_h3.c17 [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)),
A Dclk_h616.c16 [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31) | BIT(27)),
/u-boot/arch/arm/dts/
A Dsun50i-h616.dtsi682 <&ccu CLK_PLL_PERIPH0>;
A Dsunxi-h3-h5.dtsi886 <&ccu CLK_PLL_PERIPH0>;
A Dsun50i-h6.dtsi936 <&ccu CLK_PLL_PERIPH0>;
A Dsun9i-a80.dtsi226 <&ccu CLK_PLL_PERIPH0>,
A Dsun50i-a64.dtsi1291 <&ccu CLK_PLL_PERIPH0>;

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