Searched refs:CLK_TOP_AXI_SEL (Results 1 – 10 of 10) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7623.c | 599 GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
611 GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16),
650 GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
658 GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9),
667 GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18),
672 GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23),
673 GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
674 GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
675 GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
684 GATE_PERI1(CLK_PERI_GCPU, CLK_TOP_AXI_SEL, 2),
[all …]
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| A D | clk-mt8512.c | 451 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents,
728 GATE_INFRA1(CLK_INFRA_APXGPT, CLK_TOP_AXI_SEL, 6),
729 GATE_INFRA1(CLK_INFRA_ICUSB, CLK_TOP_AXI_SEL, 8),
730 GATE_INFRA1(CLK_INFRA_GCE, CLK_TOP_AXI_SEL, 9),
731 GATE_INFRA1(CLK_INFRA_THERM, CLK_TOP_AXI_SEL, 10),
745 GATE_INFRA1(CLK_INFRA_BTIF, CLK_TOP_AXI_SEL, 31),
749 GATE_INFRA2(CLK_INFRA_MSDC1, CLK_TOP_AXI_SEL, 4),
751 GATE_INFRA2(CLK_INFRA_GCPU, CLK_TOP_AXI_SEL, 8),
752 GATE_INFRA2(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 9),
764 GATE_INFRA3(CLK_INFRA_SPIS, CLK_TOP_AXI_SEL, 6),
[all …]
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| A D | clk-mt7622.c | 386 GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
424 GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
436 GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17),
440 GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
441 GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
442 GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
443 GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
448 GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
484 GATE_PCIE(CLK_SATA_AHB_EN, CLK_TOP_AXI_SEL, 26),
550 GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
[all …]
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| A D | clk-mt7629.c | 135 FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1),
136 FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1),
145 FACTOR1(CLK_TOP_TO_USB3_MCU, CLK_TOP_AXI_SEL, 1, 1),
147 FACTOR1(CLK_TOP_FROM_TOP_AHB, CLK_TOP_AXI_SEL, 1, 1),
366 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
571 .muxes_offs = CLK_TOP_AXI_SEL,
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| /u-boot/arch/arm/dts/ |
| A D | mt7629.dtsi | 187 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
199 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
212 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
223 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
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| A D | mt7622.dtsi | 46 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
176 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
196 <&topckgen CLK_TOP_AXI_SEL>;
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 87 #define CLK_TOP_AXI_SEL 73 macro
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| A D | mt8512-clk.h | 69 #define CLK_TOP_AXI_SEL 58 macro
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| A D | mt7622-clk.h | 69 #define CLK_TOP_AXI_SEL 56 macro
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| A D | mt7623-clk.h | 101 #define CLK_TOP_AXI_SEL 87 macro
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