Searched refs:CLK_TOP_DDRPHYCFG_SEL (Results 1 – 11 of 11) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 89 #define CLK_TOP_DDRPHYCFG_SEL 75 macro
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| A D | mt8516-clk.h | 86 #define CLK_TOP_DDRPHYCFG_SEL 62 macro
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| A D | mt7622-clk.h | 71 #define CLK_TOP_DDRPHYCFG_SEL 58 macro
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| A D | mt8518-clk.h | 93 #define CLK_TOP_DDRPHYCFG_SEL 71 macro
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| A D | mt7623-clk.h | 103 #define CLK_TOP_DDRPHYCFG_SEL 89 macro
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| /u-boot/arch/arm/dts/ |
| A D | mt7629.dtsi | 119 clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7629.c | 368 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
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| A D | clk-mt8516.c | 510 MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
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| A D | clk-mt7622.c | 315 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
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| A D | clk-mt7623.c | 512 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
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| A D | clk-mt8518.c | 1190 MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
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Completed in 31 milliseconds