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Searched refs:CLK_TOP_IRRX_SEL (Results 1 – 4 of 4) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h113 #define CLK_TOP_IRRX_SEL 99 macro
A Dmt7622-clk.h95 #define CLK_TOP_IRRX_SEL 82 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c352 MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23),
388 GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16),
A Dclk-mt7629.c405 MUX_GATE(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23),

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