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Searched refs:CLK_TOP_IRTX_SEL (Results 1 – 4 of 4) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h114 #define CLK_TOP_IRTX_SEL 100 macro
A Dmt7622-clk.h96 #define CLK_TOP_IRTX_SEL 83 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c353 MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31),
453 GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2),
A Dclk-mt7629.c406 MUX_GATE(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31),

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