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Searched refs:CLK_TOP_SYSPLL_D5 (Results 1 – 10 of 10) sorted by relevance

/u-boot/drivers/clk/mediatek/
A Dclk-mt7623.c106 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
115 FACTOR1(CLK_TOP_SYSPLL3_D2, CLK_TOP_SYSPLL_D5, 1, 2),
116 FACTOR1(CLK_TOP_SYSPLL3_D4, CLK_TOP_SYSPLL_D5, 1, 4),
191 CLK_TOP_SYSPLL_D5,
230 CLK_TOP_SYSPLL_D5,
430 CLK_TOP_SYSPLL_D5
442 CLK_TOP_SYSPLL_D5,
460 CLK_TOP_SYSPLL_D5,
A Dclk-mt8183.c86 FACTOR(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1,
104 FACTOR(CLK_TOP_SYSPLL_D5_D2, CLK_TOP_SYSPLL_D5, 1,
106 FACTOR(CLK_TOP_SYSPLL_D5_D4, CLK_TOP_SYSPLL_D5, 1,
413 CLK_TOP_SYSPLL_D5
477 CLK_TOP_SYSPLL_D5,
A Dclk-mt7629.c110 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
156 CLK_TOP_SYSPLL_D5,
315 CLK_TOP_SYSPLL_D5
354 CLK_TOP_SYSPLL_D5,
A Dclk-mt8512.c86 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
251 CLK_TOP_SYSPLL_D5
336 CLK_TOP_SYSPLL_D5,
410 CLK_TOP_SYSPLL_D5,
A Dclk-mt7622.c108 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
145 CLK_TOP_SYSPLL_D5,
277 CLK_TOP_SYSPLL_D5
301 CLK_TOP_SYSPLL_D5,
/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h45 #define CLK_TOP_SYSPLL_D5 32 macro
A Dmt8512-clk.h21 #define CLK_TOP_SYSPLL_D5 10 macro
A Dmt7622-clk.h36 #define CLK_TOP_SYSPLL_D5 24 macro
A Dmt8183-clk.h44 #define CLK_TOP_SYSPLL_D5 8 macro
A Dmt7623-clk.h31 #define CLK_TOP_SYSPLL_D5 18 macro

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