Home
last modified time | relevance | path

Searched refs:CPLD_READ (Results 1 – 22 of 22) sorted by relevance

/u-boot/board/freescale/t104xrdb/
A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
A Dt104xrdb.c43 CPLD_READ(hw_ver), CPLD_READ(sw_ver)); in checkboard()
45 sw = CPLD_READ(flash_ctl_status); in checkboard()
105 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | in misc_init_r()
110 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | in misc_init_r()
A Dcpld.h40 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) macro
/u-boot/board/freescale/t102xrdb/
A Dcpld.c34 u8 reg = CPLD_READ(flash_csr); in cpld_set_altbank()
47 u8 reg = CPLD_READ(flash_csr); in cpld_set_defbank()
57 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
58 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
59 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
60 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
61 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
62 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
63 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
64 printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr)); in cpld_dump_regs()
[all …]
A Dt102xrdb.c61 CPLD_READ(hw_ver), CPLD_READ(sw_ver)); in checkboard()
74 reg = CPLD_READ(flash_csr); in checkboard()
104 u8 reg = CPLD_READ(misc_ctl_status); in board_mux_lane()
A Dcpld.h32 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) macro
/u-boot/board/freescale/t4rdb/
A Dcpld.c44 val = CPLD_READ(vbank); in cpld_set_altbank()
52 override = CPLD_READ(software_on); in cpld_set_altbank()
77 printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1)); in cpld_dump_regs()
78 printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2)); in cpld_dump_regs()
79 printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver)); in cpld_dump_regs()
80 printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver)); in cpld_dump_regs()
81 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
84 printf("res0 = 0x%02x\n", CPLD_READ(res0)); in cpld_dump_regs()
85 printf("vbank = 0x%02x\n", CPLD_READ(vbank)); in cpld_dump_regs()
90 printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset)); in cpld_dump_regs()
[all …]
A Dt4240rdb.c38 CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver)); in checkboard()
40 sw = CPLD_READ(vbank); in checkboard()
162 sw = CPLD_READ(vbank); in cs4340_get_fw_addr()
A Dcpld.h45 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) macro
/u-boot/board/freescale/ls1046ardb/
A Dcpld.c31 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_altbank()
34 u8 reg7 = CPLD_READ(vbank); in cpld_set_altbank()
53 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_defbank()
96 printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
98 printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); in cpld_dump_regs()
102 printf("vbank = %x\n", CPLD_READ(vbank)); in cpld_dump_regs()
103 printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); in cpld_dump_regs()
104 printf("uart_sel = %x\n", CPLD_READ(uart_sel)); in cpld_dump_regs()
109 printf("sd_emmc = %x\n", CPLD_READ(sd_emmc)); in cpld_dump_regs()
110 printf("vdd_en = %x\n", CPLD_READ(vdd_en)); in cpld_dump_regs()
[all …]
A Dls1046ardb.c58 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); in checkboard()
59 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); in checkboard()
65 printf("QSPI vBank %d\n", CPLD_READ(vbank)); in checkboard()
71 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), in checkboard()
72 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); in checkboard()
75 sd1refclk_sel = CPLD_READ(sd1refclk_sel); in checkboard()
A Dcpld.h39 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) macro
/u-boot/board/freescale/p2041rdb/
A Dcpld.c51 u8 reg5 = CPLD_READ(sw_ctl_on); in __cpld_set_altbank()
73 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
75 printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); in cpld_dump_regs()
76 printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); in cpld_dump_regs()
77 printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); in cpld_dump_regs()
78 printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); in cpld_dump_regs()
80 printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel)); in cpld_dump_regs()
81 printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk)); in cpld_dump_regs()
83 printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel)); in cpld_dump_regs()
84 printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux)); in cpld_dump_regs()
[all …]
A Dp2041rdb.c38 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver), in checkboard()
39 CPLD_READ(cpld_ver_sub)); in checkboard()
41 sw = CPLD_READ(fbank_sel); in checkboard()
154 u8 sysclk_conf = CPLD_READ(sysclk_sw1); in get_board_sys_clk()
199 if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) && in misc_init_r()
200 (CPLD_READ(pcba_ver) == 5)) { in misc_init_r()
A Dcpld.h53 #define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg)) macro
A Deth.c51 u8 mux = CPLD_READ(serdes_mux); in initialize_lane_to_slot()
/u-boot/board/freescale/ls1043ardb/
A Dcpld.c31 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_altbank()
34 u8 reg7 = CPLD_READ(vbank); in cpld_set_altbank()
53 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_defbank()
73 if (CPLD_READ(cpld_ver) > 0x2) in cpld_set_nand()
107 printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
109 printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); in cpld_dump_regs()
110 printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); in cpld_dump_regs()
113 printf("vbank = %x\n", CPLD_READ(vbank)); in cpld_dump_regs()
114 printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); in cpld_dump_regs()
115 printf("uart_sel = %x\n", CPLD_READ(uart_sel)); in cpld_dump_regs()
[all …]
A Dls1043ardb.c162 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); in checkboard()
163 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); in checkboard()
169 printf("vBank %d\n", CPLD_READ(vbank)); in checkboard()
179 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), in checkboard()
180 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); in checkboard()
183 sd1refclk_sel = CPLD_READ(sd1refclk_sel); in checkboard()
285 if (CPLD_READ(pcba_ver) < 0x7) in fdt_fixup_phy_addr()
354 if (CPLD_READ(pcba_ver) < 0x7) in nand_fixup()
369 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); in nand_fixup()
370 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); in nand_fixup()
A Dcpld.h34 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) macro
/u-boot/board/freescale/t208xrdb/
A Dt208xrdb.c32 u8 ver = CPLD_READ(hw_ver); in get_hw_revision()
52 get_hw_revision(), CPLD_READ(sw_ver)); in checkboard()
61 reg = CPLD_READ(flash_csr); in checkboard()
117 reg = CPLD_READ(reset_ctl); in misc_init_r()
123 reg = CPLD_READ(misc_csr); in misc_init_r()
166 reg = CPLD_READ(flash_csr); in cs4340_get_fw_addr()
A Dcpld.c29 u8 reg = CPLD_READ(flash_csr); in cpld_set_altbank()
39 u8 reg = CPLD_READ(flash_csr); in cpld_set_defbank()
A Dcpld.h30 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) macro

Completed in 30 milliseconds