Searched refs:CPLL (Results 1 – 14 of 14) sorted by relevance
| /u-boot/arch/arm/mach-exynos/include/mach/ |
| A D | clk.h | 18 #define CPLL 8 macro
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| /u-boot/include/dt-bindings/clock/ |
| A D | xlnx-versal-clk.h | 35 #define CPLL 26 macro
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | cru_rk3368.h | 18 CPLL, enumerator
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| A D | cru_px30.h | 26 CPLL, enumerator
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| A D | cru_rv1126.h | 48 CPLL, enumerator
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| A D | cru_rk3568.h | 23 CPLL, enumerator
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| A D | cru_rk3588.h | 26 CPLL, enumerator
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rk3368.c | 147 rkclk_set_pll(cru, CPLL, &cpll_init_cfg); in rkclk_init()
153 cpll = rkclk_pll_get_rate(cru, CPLL); in rkclk_init()
190 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
465 rate = rkclk_pll_get_rate(priv->cru, CPLL); in rk3368_clk_get_rate()
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| A D | clk_rk3588.c | 60 [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3588_PLL_CON(104),
1491 rate = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_get_rate()
1492 CPLL); in rk3588_clk_get_rate()
1642 ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_set_rate()
1643 CPLL, rate); in rk3588_clk_set_rate()
1644 priv->cpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], in rk3588_clk_set_rate()
1645 priv->cru, CPLL); in rk3588_clk_set_rate()
1903 ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_init()
1904 CPLL, CPLL_HZ); in rk3588_clk_init()
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| A D | clk_px30.c | 783 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); in px30_vop_get_clk()
822 rkclk_set_pll(&cru->pll[CPLL], &cru->mode, in px30_vop_set_clk()
823 CPLL, hz * src_clk_div); in px30_vop_set_clk()
1091 pll_rate = px30_clk_get_pll_rate(priv, CPLL); in px30_mac_set_clk()
1206 rate = px30_clk_get_pll_rate(priv, CPLL); in px30_clk_get_rate()
1295 ret = px30_clk_set_pll_rate(priv, CPLL, rate); in px30_clk_set_rate()
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| A D | clk_rv1126.c | 66 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126_PLL_CON(16),
1428 rate = rockchip_pll_get_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_get_rate()
1429 CPLL); in rv1126_clk_get_rate()
1538 ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_set_rate()
1539 CPLL, rate); in rv1126_clk_set_rate()
1793 ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_init()
1794 CPLL, CPLL_HZ); in rv1126_clk_init()
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| A D | clk_rk3568.c | 82 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3568_PLL_CON(24),
2342 rate = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], priv->cru, in rk3568_clk_get_rate()
2343 CPLL); in rk3568_clk_get_rate()
2518 ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru, in rk3568_clk_set_rate()
2519 CPLL, rate); in rk3568_clk_set_rate()
2520 priv->cpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], in rk3568_clk_set_rate()
2521 priv->cru, CPLL); in rk3568_clk_set_rate()
2877 ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru, in rk3568_clk_init()
2878 CPLL, CPLL_HZ); in rk3568_clk_init()
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| /u-boot/arch/arm/mach-exynos/ |
| A D | clock.c | 1051 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, in exynos5800_get_lcd_clk()
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| /u-boot/arch/arm/dts/ |
| A D | rk3328.dtsi | 771 * CPLL should run at 1200, but that is to high for
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