CSITE_CPU_DBG0_LAR (reference) in projects: u-boot

Searched refs:CSITE_CPU_DBG0_LAR (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/include/asm/arch-tegra/
A D	ap.h	`30 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) macro`
/u-boot/arch/arm/mach-tegra/
A D	cpu.h	`40 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) macro`
A D	cpu.c	`441 writel(rst, CSITE_CPU_DBG0_LAR); in clock_enable_coresight()`
/u-boot/arch/arm/mach-tegra/tegra20/
A D	warmboot_avp.c	`134 writel(reg, CSITE_CPU_DBG0_LAR); in wb_start()`

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