1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018-2022 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) type definitions for 6 * Octeon xcv. 7 */ 8 9 #ifndef __CVMX_XCV_DEFS_H__ 10 #define __CVMX_XCV_DEFS_H__ 11 12 #define CVMX_XCV_BATCH_CRD_RET (0x00011800DB000100ull) 13 #define CVMX_XCV_COMP_CTL (0x00011800DB000020ull) 14 #define CVMX_XCV_CTL (0x00011800DB000030ull) 15 #define CVMX_XCV_DLL_CTL (0x00011800DB000010ull) 16 #define CVMX_XCV_ECO (0x00011800DB000200ull) 17 #define CVMX_XCV_INBND_STATUS (0x00011800DB000080ull) 18 #define CVMX_XCV_INT (0x00011800DB000040ull) 19 #define CVMX_XCV_RESET (0x00011800DB000000ull) 20 21 /** 22 * cvmx_xcv_batch_crd_ret 23 */ 24 union cvmx_xcv_batch_crd_ret { 25 u64 u64; 26 struct cvmx_xcv_batch_crd_ret_s { 27 u64 reserved_1_63 : 63; 28 u64 crd_ret : 1; 29 } s; 30 struct cvmx_xcv_batch_crd_ret_s cn73xx; 31 }; 32 33 typedef union cvmx_xcv_batch_crd_ret cvmx_xcv_batch_crd_ret_t; 34 35 /** 36 * cvmx_xcv_comp_ctl 37 * 38 * This register controls programmable compensation. 39 * 40 */ 41 union cvmx_xcv_comp_ctl { 42 u64 u64; 43 struct cvmx_xcv_comp_ctl_s { 44 u64 drv_byp : 1; 45 u64 reserved_61_62 : 2; 46 u64 cmp_pctl : 5; 47 u64 reserved_53_55 : 3; 48 u64 cmp_nctl : 5; 49 u64 reserved_45_47 : 3; 50 u64 drv_pctl : 5; 51 u64 reserved_37_39 : 3; 52 u64 drv_nctl : 5; 53 u64 reserved_31_31 : 1; 54 u64 pctl_lock : 1; 55 u64 pctl_sat : 1; 56 u64 reserved_28_28 : 1; 57 u64 nctl_lock : 1; 58 u64 reserved_1_26 : 26; 59 u64 nctl_sat : 1; 60 } s; 61 struct cvmx_xcv_comp_ctl_s cn73xx; 62 }; 63 64 typedef union cvmx_xcv_comp_ctl cvmx_xcv_comp_ctl_t; 65 66 /** 67 * cvmx_xcv_ctl 68 * 69 * This register contains the status control bits. 70 * 71 */ 72 union cvmx_xcv_ctl { 73 u64 u64; 74 struct cvmx_xcv_ctl_s { 75 u64 reserved_4_63 : 60; 76 u64 lpbk_ext : 1; 77 u64 lpbk_int : 1; 78 u64 speed : 2; 79 } s; 80 struct cvmx_xcv_ctl_s cn73xx; 81 }; 82 83 typedef union cvmx_xcv_ctl cvmx_xcv_ctl_t; 84 85 /** 86 * cvmx_xcv_dll_ctl 87 * 88 * The RGMII timing specification requires that devices transmit clock and 89 * data synchronously. The specification requires external sources (namely 90 * the PC board trace routes) to introduce the appropriate 1.5 to 2.0 ns of 91 * delay. 92 * 93 * To eliminate the need for the PC board delays, the RGMII interface has optional 94 * on-board DLLs for both transmit and receive. For correct operation, at most one 95 * of the transmitter, board, or receiver involved in an RGMII link should 96 * introduce delay. By default/reset, the RGMII receivers delay the received clock, 97 * and the RGMII transmitters do not delay the transmitted clock. Whether this 98 * default works as-is with a given link partner depends on the behavior of the 99 * link partner and the PC board. 100 * 101 * These are the possible modes of RGMII receive operation: 102 * 103 * * XCV_DLL_CTL[CLKRX_BYP] = 0 (reset value) - The RGMII 104 * receive interface introduces clock delay using its internal DLL. 105 * This mode is appropriate if neither the remote 106 * transmitter nor the PC board delays the clock. 107 * 108 * * XCV_DLL_CTL[CLKRX_BYP] = 1, [CLKRX_SET] = 0x0 - The 109 * RGMII receive interface introduces no clock delay. This mode 110 * is appropriate if either the remote transmitter or the PC board 111 * delays the clock. 112 * 113 * These are the possible modes of RGMII transmit operation: 114 * 115 * * XCV_DLL_CTL[CLKTX_BYP] = 1, [CLKTX_SET] = 0x0 (reset value) - 116 * The RGMII transmit interface introduces no clock 117 * delay. This mode is appropriate is either the remote receiver 118 * or the PC board delays the clock. 119 * 120 * * XCV_DLL_CTL[CLKTX_BYP] = 0 - The RGMII transmit 121 * interface introduces clock delay using its internal DLL. 122 * This mode is appropriate if neither the remote receiver 123 * nor the PC board delays the clock. 124 */ 125 union cvmx_xcv_dll_ctl { 126 u64 u64; 127 struct cvmx_xcv_dll_ctl_s { 128 u64 reserved_32_63 : 32; 129 u64 lock : 1; 130 u64 clk_set : 7; 131 u64 clkrx_byp : 1; 132 u64 clkrx_set : 7; 133 u64 clktx_byp : 1; 134 u64 clktx_set : 7; 135 u64 reserved_2_7 : 6; 136 u64 refclk_sel : 2; 137 } s; 138 struct cvmx_xcv_dll_ctl_s cn73xx; 139 }; 140 141 typedef union cvmx_xcv_dll_ctl cvmx_xcv_dll_ctl_t; 142 143 /** 144 * cvmx_xcv_eco 145 */ 146 union cvmx_xcv_eco { 147 u64 u64; 148 struct cvmx_xcv_eco_s { 149 u64 reserved_16_63 : 48; 150 u64 eco_rw : 16; 151 } s; 152 struct cvmx_xcv_eco_s cn73xx; 153 }; 154 155 typedef union cvmx_xcv_eco cvmx_xcv_eco_t; 156 157 /** 158 * cvmx_xcv_inbnd_status 159 * 160 * This register contains RGMII in-band status. 161 * 162 */ 163 union cvmx_xcv_inbnd_status { 164 u64 u64; 165 struct cvmx_xcv_inbnd_status_s { 166 u64 reserved_4_63 : 60; 167 u64 duplex : 1; 168 u64 speed : 2; 169 u64 link : 1; 170 } s; 171 struct cvmx_xcv_inbnd_status_s cn73xx; 172 }; 173 174 typedef union cvmx_xcv_inbnd_status cvmx_xcv_inbnd_status_t; 175 176 /** 177 * cvmx_xcv_int 178 * 179 * This register controls interrupts. 180 * 181 */ 182 union cvmx_xcv_int { 183 u64 u64; 184 struct cvmx_xcv_int_s { 185 u64 reserved_7_63 : 57; 186 u64 tx_ovrflw : 1; 187 u64 tx_undflw : 1; 188 u64 incomp_byte : 1; 189 u64 duplex : 1; 190 u64 reserved_2_2 : 1; 191 u64 speed : 1; 192 u64 link : 1; 193 } s; 194 struct cvmx_xcv_int_s cn73xx; 195 }; 196 197 typedef union cvmx_xcv_int cvmx_xcv_int_t; 198 199 /** 200 * cvmx_xcv_reset 201 * 202 * This register controls reset. 203 * 204 */ 205 union cvmx_xcv_reset { 206 u64 u64; 207 struct cvmx_xcv_reset_s { 208 u64 enable : 1; 209 u64 reserved_16_62 : 47; 210 u64 clkrst : 1; 211 u64 reserved_12_14 : 3; 212 u64 dllrst : 1; 213 u64 reserved_8_10 : 3; 214 u64 comp : 1; 215 u64 reserved_4_6 : 3; 216 u64 tx_pkt_rst_n : 1; 217 u64 tx_dat_rst_n : 1; 218 u64 rx_pkt_rst_n : 1; 219 u64 rx_dat_rst_n : 1; 220 } s; 221 struct cvmx_xcv_reset_s cn73xx; 222 }; 223 224 typedef union cvmx_xcv_reset cvmx_xcv_reset_t; 225 226 #endif 227