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Searched refs:DIV_ROUND_UP (Results 1 – 25 of 177) sorted by relevance

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/u-boot/drivers/ddr/microchip/
A Dddr2.c150 wr2rd = max_t(u32, DIV_ROUND_UP(T_WTR, T_CK_CTRL), in ddr2_ctrl_init()
151 DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL; in ddr2_ctrl_init()
153 wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL; in ddr2_ctrl_init()
155 DIV_ROUND_UP(T_RTP_TCK, 2)) + BL - 2; in ddr2_ctrl_init()
157 DIV_ROUND_UP(T_RRD_TCK, 2)) - 1; in ddr2_ctrl_init()
158 ras2cas = DIV_ROUND_UP(T_RCD, T_CK_CTRL) - 1; in ddr2_ctrl_init()
159 prech2ras = DIV_ROUND_UP(T_RP, T_CK_CTRL) - 1; in ddr2_ctrl_init()
180 writel((DIV_ROUND_UP(T_RP, T_CK_CTRL) | in ddr2_ctrl_init()
188 writel(((DIV_ROUND_UP(T_RAS_MIN, T_CK_CTRL) - 1) | in ddr2_ctrl_init()
189 ((DIV_ROUND_UP(T_RC, T_CK_CTRL) - 1) << 8) | in ddr2_ctrl_init()
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/u-boot/drivers/phy/
A Dmeson-axg-mipi-dphy.c236 DIV_ROUND_UP(priv->config.clk_trail, temp) | in phy_meson_axg_mipi_dphy_power_on()
237 (DIV_ROUND_UP(priv->config.clk_post + in phy_meson_axg_mipi_dphy_power_on()
239 (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) | in phy_meson_axg_mipi_dphy_power_on()
242 DIV_ROUND_UP(priv->config.clk_pre, temp)); in phy_meson_axg_mipi_dphy_power_on()
245 DIV_ROUND_UP(priv->config.hs_exit, temp) | in phy_meson_axg_mipi_dphy_power_on()
246 (DIV_ROUND_UP(priv->config.hs_trail, temp) << 8) | in phy_meson_axg_mipi_dphy_power_on()
247 (DIV_ROUND_UP(priv->config.hs_zero, temp) << 16) | in phy_meson_axg_mipi_dphy_power_on()
251 DIV_ROUND_UP(priv->config.lpx, temp) | in phy_meson_axg_mipi_dphy_power_on()
252 (DIV_ROUND_UP(priv->config.ta_sure, temp) << 8) | in phy_meson_axg_mipi_dphy_power_on()
253 (DIV_ROUND_UP(priv->config.ta_go, temp) << 16) | in phy_meson_axg_mipi_dphy_power_on()
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/u-boot/arch/arm/mach-imx/mx6/
A Dddr.c1095 txp = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1098 tfaw = DIV_ROUND_UP(60000, clkper) - 1; in mx6_lpddr2_cfg()
1100 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_lpddr2_cfg()
1101 trrd = DIV_ROUND_UP(10000, clkper) - 1; in mx6_lpddr2_cfg()
1104 tcksre = DIV_ROUND_UP(15000, clkper); in mx6_lpddr2_cfg()
1106 twr = DIV_ROUND_UP(15000, clkper) - 1; in mx6_lpddr2_cfg()
1121 twtr = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1122 trtp = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1333 txs = DIV_ROUND_UP(120000, clkper) - 1; in mx6_ddr3_cfg()
1337 txs = DIV_ROUND_UP(170000, clkper) - 1; in mx6_ddr3_cfg()
[all …]
/u-boot/drivers/clk/rockchip/
A Dclk_rv1108.c164 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_mac_set_clk()
185 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_sfc_set_clk()
210 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rv1108_saradc_set_clk()
235 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio1_set_clk()
261 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio0_set_clk()
296 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_dclk_vop_set_clk()
326 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_bus_set_clk()
378 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_peri_set_clk()
394 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_hclk_peri_set_clk()
409 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_pclk_peri_set_clk()
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A Dclk_px30.c117 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_clk_set_by_auto()
118 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_clk_set_by_auto()
324 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_i2c_set_clk()
637 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_pwm_set_clk()
679 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_saradc_set_clk()
705 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_tsadc_set_clk()
742 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_spi_set_clk()
966 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_peri_set_clk()
1024 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_crypto_set_clk()
1101 div = DIV_ROUND_UP(pll_rate, hz) - 1; in px30_mac_set_clk()
[all …]
A Dclk_rv1126.c218 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_i2c_set_pmuclk()
332 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_spi_set_pmuclk()
360 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdpmu_set_pmuclk()
583 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdcore_set_clk()
715 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdphp_set_clk()
754 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdaudio_set_clk()
798 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_i2c_set_clk()
841 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_spi_set_clk()
903 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rv1126_saradc_set_clk()
1062 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, rate); in rv1126_mmc_set_clk()
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A Dclk_rk3588.c789 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_mmc_set_clk()
810 div = DIV_ROUND_UP(702 * MHz, rate); in rk3588_mmc_set_clk()
895 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_aux16m_set_clk()
1153 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1212 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_gmac_set_clk()
1318 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_uart_set_rate()
1322 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_uart_set_rate()
1896 div = DIV_ROUND_UP(GPLL_HZ, 300 * MHz); in rk3588_clk_init()
2066 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_scru_clk_set_rate()
2069 div = DIV_ROUND_UP(SPLL_HZ, rate); in rk3588_scru_clk_set_rate()
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A Dclk_rk3308.c164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
214 div = DIV_ROUND_UP(pll_rate, hz) - 1; in rk3308_mac_set_clk()
328 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk3308_saradc_set_clk()
356 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk3308_tsadc_set_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
513 div = DIV_ROUND_UP(pll_rate, hz); in rk3308_vop_set_clk()
577 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_bus_set_clk()
640 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_peri_set_clk()
699 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz); in rk3308_audio_set_clk()
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A Dclk_rk3288.c249 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); in pll_para_config()
251 *ext_div = DIV_ROUND_UP(no, max_no); in pll_para_config()
252 no = DIV_ROUND_UP(no, *ext_div); in pll_para_config()
257 no = DIV_ROUND_UP(no, 2) * 2; in pll_para_config()
330 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rockchip_mac_set_clk()
619 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); in rockchip_mmc_set_clk()
622 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
697 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; in rockchip_spi_set_clk()
740 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rockchip_saradc_set_clk()
A Dclk_rk3128.c96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
98 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
99 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_para_config()
320 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); in rockchip_mmc_set_clk()
323 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
410 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3128_saradc_set_clk()
/u-boot/board/freescale/common/
A Dvid.c237 voltage_read = DIV_ROUND_UP(voltage_read, 128); in read_voltage_from_IR()
337 vout = DIV_ROUND_UP(vout * MV_PER_V, multiplier); in read_voltage_from_pmbus()
436 vid = DIV_ROUND_UP(vdd - 265, 5); in set_voltage_to_IR()
438 vid = DIV_ROUND_UP(vdd - 245, 5); in set_voltage_to_IR()
481 vdd = DIV_ROUND_UP(vdd * multiplier, MV_PER_V); in set_voltage_to_pmbus()
645 DIV_ROUND_UP(vdd_target, 10)); in adjust_vdd()
661 vdd_target = DIV_ROUND_UP(vdd_target, 10); in adjust_vdd()
/u-boot/include/linux/
A Ddelay.h18 udelay(DIV_ROUND_UP(nsec, 1000)); in ndelay()
/u-boot/drivers/phy/rockchip/
A Dphy-rockchip-inno-dsidphy.c332 min_prediv = DIV_ROUND_UP(fref, 40000000); in inno_dsidphy_pll_calc_rate()
430 esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000); in inno_dsidphy_mipi_mode_enable()
438 hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs); in inno_dsidphy_mipi_mode_enable()
443 clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs); in inno_dsidphy_mipi_mode_enable()
448 clk_pre = DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE); in inno_dsidphy_mipi_mode_enable()
455 ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc); in inno_dsidphy_mipi_mode_enable()
461 ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc); in inno_dsidphy_mipi_mode_enable()
467 ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc); in inno_dsidphy_mipi_mode_enable()
481 lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs); in inno_dsidphy_mipi_mode_enable()
/u-boot/drivers/i2c/
A Dast2600_i2c.c204 divisor = DIV_ROUND_UP(apb_clk, speed); in ast2600_i2c_set_speed()
207 divisor = DIV_ROUND_UP(base_clk1, speed); in ast2600_i2c_set_speed()
210 divisor = DIV_ROUND_UP(base_clk2, speed); in ast2600_i2c_set_speed()
213 divisor = DIV_ROUND_UP(base_clk3, speed); in ast2600_i2c_set_speed()
216 divisor = DIV_ROUND_UP(base_clk4, speed); in ast2600_i2c_set_speed()
A Dsynquacer_i2c.c62 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_SPEED_STANDARD_RATE) - 2, 2)
65 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_SPEED_FAST_RATE) - 2) * 2, 3)
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dppa.c102 cnt = DIV_ROUND_UP(fdt_header_len, 512); in ppa_init()
128 cnt = DIV_ROUND_UP(CONFIG_LS_PPA_ESBC_HDR_SIZE, 512); in ppa_init()
152 cnt = DIV_ROUND_UP(fw_length, 512); in ppa_init()
/u-boot/fs/squashfs/
A Dsqfs_inode.c36 blk_list_size = DIV_ROUND_UP(file_size, blk_size); in sqfs_inode_size()
72 blk_list_size = DIV_ROUND_UP(file_size, blk_size); in sqfs_inode_size()
/u-boot/arch/x86/include/asm/
A Ditss.h21 #define NUM_IPC_REGS DIV_ROUND_UP(ITSS_MAX_IRQ, IRQS_PER_IPC)
/u-boot/drivers/fpga/
A Dsocfpga.c52 uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4); in fpgamgr_program_write()
/u-boot/lib/aes/
A Daes-decrypt.c34 aes_blocks = DIV_ROUND_UP(cipher_len, AES_BLOCK_LENGTH); in image_aes_decrypt()
/u-boot/drivers/mtd/onenand/
A Donenand_spl.c185 to_page = page + DIV_ROUND_UP(size, 2048); in onenand_spl_load_image()
188 to_page = page + DIV_ROUND_UP(size, 4096); in onenand_spl_load_image()
/u-boot/tools/
A Domapimage.c22 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) macro
155 DIV_ROUND_UP(sbuf->st_size, sizeof(uint32_t)); in omapimage_set_header()
/u-boot/drivers/clk/ti/
A Dclk-divider.c97 return DIV_ROUND_UP(parent_rate, rate); in _div_round()
149 r = DIV_ROUND_UP(parent_round_rate, i); in clk_ti_divider_best_div()
181 return DIV_ROUND_UP(parent_rate, div); in clk_ti_divider_round_rate()
234 rate = DIV_ROUND_UP(parent_rate, div); in clk_ti_divider_get_rate()
/u-boot/drivers/mmc/
A Dsdhci-adma.c46 uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN); in sdhci_prepare_adma_table()
/u-boot/drivers/watchdog/
A Dsandbox_alarm-wdt.c25 timeout = DIV_ROUND_UP(timeout, 1000); in alarm_wdt_start()

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