| /u-boot/arch/mips/mach-mtmips/include/mach/ |
| A D | mc.h | 141 #define DLL 0x01 macro
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| /u-boot/board/Seagate/nas220/ |
| A D | kwbimage.cfg | 92 # bit8: 0, DLL reset=0 normal
99 # bit0: 0, DDR DLL enabled
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| /u-boot/board/Marvell/dreamplug/ |
| A D | kwbimage.cfg | 88 # bit8: 0, DLL reset=0 normal
94 # bit0: 0, DDR DLL enabled
|
| /u-boot/board/Marvell/sheevaplug/ |
| A D | kwbimage.cfg | 87 # bit8: 0, DLL reset=0 normal
93 # bit0: 0, DDR DLL enabled
|
| /u-boot/board/Synology/ds109/ |
| A D | kwbimage.cfg | 91 # bit8: 0, DLL reset=0 normal
97 # bit0: 0, DDR DLL enabled
|
| /u-boot/board/cloudengines/pogo_v4/ |
| A D | kwbimage.cfg | 88 # bit8: 0, DLL reset=0 normal
94 # bit0: 0, DDR DLL enabled
|
| /u-boot/board/Marvell/guruplug/ |
| A D | kwbimage.cfg | 87 # bit8: 0, DLL reset=0 normal
93 # bit0: 0, DDR DLL enabled
|
| /u-boot/board/Seagate/dockstar/ |
| A D | kwbimage.cfg | 90 # bit8: 0, DLL reset=0 normal
96 # bit0: 0, DDR DLL enabled
|
| /u-boot/board/Seagate/goflexhome/ |
| A D | kwbimage.cfg | 93 # bit8: 0, DLL reset=0 normal
99 # bit0: 0, DDR DLL enabled
|
| /u-boot/arch/powerpc/cpu/mpc83xx/initreg/ |
| A D | Kconfig.lcrr | 6 prompt "DLL bypass"
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| /u-boot/board/iomega/iconnect/ |
| A D | kwbimage.cfg | 87 # bit8: 0x0, DLL reset=0 normal
93 # bit0: 0, DDR DLL enabled
|
| /u-boot/board/LaCie/net2big_v2/ |
| A D | kwbimage.cfg | 87 # bit8: 0, DLL reset=0 normal
93 # bit0: 0, DDR DLL enabled
|
| /u-boot/board/LaCie/netspace_v2/ |
| A D | kwbimage-is2.cfg | 87 # bit8: 0, DLL reset=0 normal
93 # bit0: 0, DDR DLL enabled
|
| A D | kwbimage-ns2l.cfg | 87 # bit8: 0, DLL reset=0 normal
93 # bit0: 0, DDR DLL enabled
|
| A D | kwbimage.cfg | 87 # bit8: 0, DLL reset=0 normal
93 # bit0: 0, DDR DLL enabled
|
| /u-boot/board/Marvell/openrd/ |
| A D | kwbimage.cfg | 87 # bit8: 0, DLL reset=0 normal
93 # bit0: 0, DDR DLL enabled
|
| /u-boot/board/cloudengines/pogo_e02/ |
| A D | kwbimage.cfg | 91 # bit8: 0, DLL reset=0 normal
97 # bit0: 0, DDR DLL enabled
|
| /u-boot/board/raidsonic/ib62x0/ |
| A D | kwbimage.cfg | 88 # bit8: 0x0, DLL reset=0 normal
94 # bit0: 0, DDR DLL enabled
|
| /u-boot/board/buffalo/lsxl/ |
| A D | kwbimage-lschl.cfg | 105 # bit8: 0, (Reset DLL) Normal operation
112 # bit0: 0, DRAM DLL enabled
|
| A D | kwbimage-lsxhl.cfg | 105 # bit8: 0, (Reset DLL) Normal operation
112 # bit0: 0, DRAM DLL enabled
|
| /u-boot/board/d-link/dns325/ |
| A D | kwbimage.cfg | 97 # bit8: 0, (Reset DLL) Normal operation
103 # bit0: 0, DRAM DLL enabled
|
| /u-boot/drivers/power/ |
| A D | Kconfig | 173 On A10(s) / A13 / A20 boards with an axp209 dcdc3 is VDD-INT-DLL and
192 On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V.
237 On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V.
239 On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC,
|
| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3288-dmc.txt | 22 …l-disable-freq: if ddr clock frequency low than dll-disable-freq,this driver should disable DDR DLL
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| /u-boot/doc/device-tree-bindings/ram/ |
| A D | fsl,mpc83xx-mem-controller.txt | 186 - dll_reset: DLL reset; possible values:
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| /u-boot/lib/lzma/ |
| A D | lzma.txt | 72 LzmaLib.* - LZMA Library for DLL calling
76 LzmaLib - LZMA Library (.DLL for Windows)
|