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Searched refs:DRAM_APB_CLK_ROOT (Results 1 – 9 of 9) sorted by relevance

/u-boot/arch/arm/include/asm/arch-imx8m/
A Dclock_imx8mm.h92 DRAM_APB_CLK_ROOT = 65, enumerator
182 DRAM_APB_CLK_ROOT = 65, enumerator
263 DRAM_APB_CLK_ROOT = 65, enumerator
A Dclock_imx8mq.h53 DRAM_APB_CLK_ROOT = 65, enumerator
/u-boot/arch/arm/include/asm/arch-imx9/
A Dccm_regs.h88 #define DRAM_APB_CLK_ROOT 77 macro
/u-boot/arch/arm/mach-imx/imx8m/
A Dclock_imx8mm.c168 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in dram_enable_bypass()
179 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in dram_disable_bypass()
485 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in clock_init()
A Dclock_imx8mq.c599 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in dram_enable_bypass()
610 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in dram_disable_bypass()
A Dclock_slice.c126 {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
585 {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
1019 {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
1383 {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
/u-boot/arch/arm/mach-imx/imx9/
A Dclock.c672 ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); in dram_enable_bypass()
680 ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); in dram_disable_bypass()
A Dclock_root.c110 { DRAM_APB_CLK_ROOT, 1 },
/u-boot/drivers/ddr/imx/imx8m/
A Dddr_init.c333 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | in ddr_init()

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