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Searched refs:FIELD_PREP (Results 1 – 25 of 62) sorted by relevance

123

/u-boot/arch/mips/mach-mtmips/mt7621/
A Dinit.c111 writel(FIELD_PREP(SSUSB_PLL_PREDIV_PE1D_M, 2) | in xhci_config_40mhz()
112 FIELD_PREP(SSUSB_PLL_PREDIV_U3_M, 1) | in xhci_config_40mhz()
113 FIELD_PREP(SSUSB_PLL_FBKDI_M, 4), in xhci_config_40mhz()
119 FIELD_PREP(SSUSB_PLL_FBKDIV_U3_M, 0x1e), in xhci_config_40mhz()
133 writel(FIELD_PREP(SSUSB_PLL_SSC_PRD_M, 0x140), in xhci_config_40mhz()
140 FIELD_PREP(SSUSB_SYSPLL_FBSEL_M, 1) | in xhci_config_40mhz()
141 FIELD_PREP(SSUSB_SYSPLL_PREDIV_M, 1), in xhci_config_40mhz()
151 FIELD_PREP(SSUSB_PCIE_SIGDET_LPF_M, 1), in xhci_config_40mhz()
173 FIELD_PREP(SSUSB_PLL_FBKDI_M, 4), in xhci_config_25mhz()
193 writel(FIELD_PREP(SSUSB_PLL_SSC_PRD_M, 0x190), in xhci_config_25mhz()
[all …]
/u-boot/drivers/phy/
A Dphy-mtk-tphy.c273 FIELD_PREP(PA0_USB20_PLL_PREDIV, 0)); in u2_phy_pll_26m_set()
276 FIELD_PREP(PA2_RG_U2PLL_BW, 3)); in u2_phy_pll_26m_set()
292 FIELD_PREP(P2C_RG_XCVRSEL, 1) | in u2_phy_instance_init()
293 FIELD_PREP(P2C_RG_DATAIN, 0)); in u2_phy_instance_init()
306 FIELD_PREP(PA6_RG_U2_SQTH, 2)); in u2_phy_instance_init()
409 FIELD_PREP(P3A_RG_CLKDRV_AMP, 0x4)); in pcie_phy_instance_init()
411 FIELD_PREP(P3A_RG_CLKDRV_OFF, 0x1)); in pcie_phy_instance_init()
479 FIELD_PREP(RG_T2_MIN_MSK, 0x12) | in sata_phy_instance_init()
480 FIELD_PREP(RG_TG_MIN_MSK, 0x04) | in sata_phy_instance_init()
481 FIELD_PREP(RG_T2_MAX_MSK, 0x31) | in sata_phy_instance_init()
[all …]
A Dphy-npcm-usb.c28 #define USBPHY2SW_DEV9_PHY1 FIELD_PREP(USBPHY2SW, 0)
29 #define USBPHY2SW_HOST1 FIELD_PREP(USBPHY2SW, 1)
30 #define USBPHY2SW_DEV9_PHY2 FIELD_PREP(USBPHY2SW, 3)
31 #define USBPHY3SW_DEV8_PHY1 FIELD_PREP(USBPHY3SW, 0)
32 #define USBPHY3SW_HOST2 FIELD_PREP(USBPHY3SW, 1)
33 #define USBPHY3SW_DEV8_PHY3 FIELD_PREP(USBPHY3SW, 3)
A Dmeson-g12a-usb3-pcie.c77 reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, addr); in phy_g12a_usb3_pcie_cr_bus_addr()
145 reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, data); in phy_g12a_usb3_pcie_cr_bus_write()
285 FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4)); in phy_meson_g12a_usb3_init()
289 FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) | in phy_meson_g12a_usb3_init()
290 FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9)); in phy_meson_g12a_usb3_init()
327 FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c)); in phy_meson_g12a_usb3_pcie_power_on()
341 FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d)); in phy_meson_g12a_usb3_pcie_power_off()
A Dmeson-axg-mipi-pcie-analog.c92 FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0x1b8)); in phy_dsi_analog_enable()
97 FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL0, 0x8)); in phy_dsi_analog_enable()
124 FIELD_PREP(HHI_MIPI_CNTL2_CH_EN, reg)); in phy_dsi_analog_enable()
133 FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0)); in phy_dsi_analog_disable()
/u-boot/drivers/net/
A Daspeed_mdio.c57 | FIELD_PREP(ASPEED_MDIO_CTRL_ST, ASPEED_MDIO_CTRL_ST_C22) in aspeed_mdio_read()
58 | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_READ) in aspeed_mdio_read()
59 | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr) in aspeed_mdio_read()
60 | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, reg); in aspeed_mdio_read()
83 | FIELD_PREP(ASPEED_MDIO_CTRL_ST, ASPEED_MDIO_CTRL_ST_C22) in aspeed_mdio_write()
84 | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_WRITE) in aspeed_mdio_write()
85 | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr) in aspeed_mdio_write()
86 | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, reg) in aspeed_mdio_write()
87 | FIELD_PREP(ASPEED_MDIO_CTRL_MIIWDATA, val); in aspeed_mdio_write()
A Dmt7620-eth.c311 val = FIELD_PREP(MDIO_ST, 1) | FIELD_PREP(MDIO_CMD, cmd) | in mt7620_mdio_rw()
312 FIELD_PREP(MDIO_PHY_ADDR, phy) | in mt7620_mdio_rw()
313 FIELD_PREP(MDIO_REG_ADDR, reg); in mt7620_mdio_rw()
316 val |= FIELD_PREP(MDIO_RW_DATA, data); in mt7620_mdio_rw()
356 FIELD_PREP(MMD_OP_MODE, MMD_ADDR) | in mt7620_mdio_read()
654 FIELD_PREP(PORT_MATRIX, 0x40)); in mt7620_gsw_set_port_isolation()
657 FIELD_PREP(PORT_MATRIX, 0x3f)); in mt7620_gsw_set_port_isolation()
701 FIELD_PREP(PORT_MATRIX, 0x40)); in mt7530_gsw_set_port_isolation()
704 FIELD_PREP(PORT_MATRIX, 0x3f)); in mt7530_gsw_set_port_isolation()
708 FIELD_PREP(STAG_VPID, 0x8100) | in mt7530_gsw_set_port_isolation()
[all …]
A Dmtk_eth.h490 #define PDMA_V1_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V1_TXD2_SDL0_M, (_v))
492 #define PDMA_V2_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V2_TXD2_SDL0_M, (_v))
495 #define PDMA_V1_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V1_TXD4_FPORT_M, (_v))
497 #define PDMA_V2_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD4_FPORT_M, (_v))
500 #define PDMA_V2_TXD5_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD5_FPORT_M, (_v))
507 #define PDMA_V1_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V1_RXD2_PLEN0_M, (_v))
510 #define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v))
A Dmdio_mux_meson_g12a.c77 writel(FIELD_PREP(PHY_CNTL1_ST_MODE, 3) | in meson_g12a_enable_internal_mdio()
78 FIELD_PREP(PHY_CNTL1_ST_PHYADD, EPHY_DFLT_ADD) | in meson_g12a_enable_internal_mdio()
79 FIELD_PREP(PHY_CNTL1_MII_MODE, EPHY_MODE_RMII) | in meson_g12a_enable_internal_mdio()
/u-boot/drivers/memory/
A Dstm32-fmc2-ebi.c393 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); in stm32_fmc2_ebi_set_trans_type()
480 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8); in stm32_fmc2_ebi_set_buswidth()
483 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16); in stm32_fmc2_ebi_set_buswidth()
534 val = FIELD_PREP(FMC2_BCR_NBLSET, val); in stm32_fmc2_ebi_set_bl_setup()
559 val = FIELD_PREP(FMC2_BXTR_ADDSET, val); in stm32_fmc2_ebi_set_address_setup()
577 val = FIELD_PREP(FMC2_BXTR_ADDHLD, val); in stm32_fmc2_ebi_set_address_hold()
595 val = FIELD_PREP(FMC2_BXTR_DATAST, val); in stm32_fmc2_ebi_set_data_setup()
613 val = FIELD_PREP(FMC2_BXTR_BUSTURN, val); in stm32_fmc2_ebi_set_bus_turnaround()
634 val = FIELD_PREP(FMC2_BXTR_DATAHLD, val); in stm32_fmc2_ebi_set_data_hold()
647 val = FIELD_PREP(FMC2_BTR_CLKDIV, val); in stm32_fmc2_ebi_set_clk_period()
[all …]
/u-boot/arch/arm/mach-apple/
A Drtkit.c141 msg->msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_BUFFER_REQUEST) | in rtkit_handle_buf_req()
142 FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, num_4kpages) | in rtkit_handle_buf_req()
143 FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, buf->dva); in rtkit_handle_buf_req()
166 FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, APPLE_RTKIT_PWR_STATE_ON); in apple_rtkit_boot()
206 FIELD_PREP(APPLE_RTKIT_MGMT_HELLO_MINVER, want_ver) | in apple_rtkit_boot()
207 FIELD_PREP(APPLE_RTKIT_MGMT_HELLO_MAXVER, want_ver); in apple_rtkit_boot()
238 reply = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_EPMAP_REPLY) | in apple_rtkit_boot()
239 FIELD_PREP(APPLE_RTKIT_MGMT_EPMAP_BASE, base); in apple_rtkit_boot()
269 msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_STARTEP) | in apple_rtkit_boot()
270 FIELD_PREP(APPLE_RTKIT_MGMT_STARTEP_EP, endpoints[i]) | in apple_rtkit_boot()
[all …]
/u-boot/drivers/spi/
A Dnpcm_fiu_spi.c113 writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, cs), &regs->uma_cts); in activate_cs()
130 writel(FIELD_PREP(UMA_CFG_RDATSIZ_MASK, size), &regs->uma_cfg); in fiu_uma_read()
166 writel(FIELD_PREP(UMA_CFG_WDATSIZ_MASK, size), &regs->uma_cfg); in fiu_uma_write()
256 FIELD_PREP(UMA_CFG_ADDSIZ_MASK, op->addr.nbytes); in npcm_fiu_uma_operation()
262 FIELD_PREP(UMA_CFG_DBSIZ_MASK, op->dummy.nbytes); in npcm_fiu_uma_operation()
267 FIELD_PREP(UMA_CFG_RDATSIZ_MASK, nbytes); in npcm_fiu_uma_operation()
270 FIELD_PREP(UMA_CFG_WDATSIZ_MASK, nbytes); in npcm_fiu_uma_operation()
398 writel(FIELD_PREP(DWR_CFG_WBURST_MASK, DWR_WBURST_16_BYTE) | in npcm_fiu_spi_bind()
399 FIELD_PREP(DWR_CFG_ADDSIZ_MASK, DWR_ADDSIZ_24_BIT) | in npcm_fiu_spi_bind()
400 FIELD_PREP(DWR_CFG_ABPCK_MASK, DWR_ABPCK_4_BIT_PER_CLK) | in npcm_fiu_spi_bind()
[all …]
A Docteon_spi.c105 FIELD_PREP(MPI_CFG_IDLELO, cpha != cpol) | in octeon_spi_set_mpicfg()
106 FIELD_PREP(MPI_CFG_CSLATE, cpha) | in octeon_spi_set_mpicfg()
238 mpi_tx = FIELD_PREP(MPI_TX_CSID, cs) | in octeon_spi_xfer()
239 FIELD_PREP(MPI_TX_LEAVECS, 1) | in octeon_spi_xfer()
241 FIELD_PREP(MPI_TX_TOTNUM, 8); in octeon_spi_xfer()
267 mpi_tx = FIELD_PREP(MPI_TX_CSID, cs) | in octeon_spi_xfer()
270 FIELD_PREP(MPI_TX_TOTNUM, len); in octeon_spi_xfer()
317 mpi_cfg |= FIELD_PREP(MPI_CFG_IOMODE, 2); in octeontx2_spi_xfer()
319 mpi_cfg |= FIELD_PREP(MPI_CFG_IOMODE, 3); in octeontx2_spi_xfer()
346 FIELD_PREP(MPI_XMIT_TOTNUM, 1024); in octeontx2_spi_xfer()
[all …]
A Dspi-sn-f-ospi.c226 val |= FIELD_PREP(OSPI_CLK_CTL_PHA, OSPI_CLK_CTL_PHA_180) in f_ospi_config_clk()
227 | FIELD_PREP(OSPI_CLK_CTL_DIV, div_reg); in f_ospi_config_clk()
274 prot |= FIELD_PREP(OSPI_PROT_MODE_CODE_MASK, mode); in f_ospi_config_indir_protocol()
277 prot |= FIELD_PREP(OSPI_PROT_MODE_ADDR_MASK, mode); in f_ospi_config_indir_protocol()
280 prot |= FIELD_PREP(OSPI_PROT_MODE_DATA_MASK, mode); in f_ospi_config_indir_protocol()
282 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_DATA, OSPI_PROT_SDR); in f_ospi_config_indir_protocol()
283 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ALT, OSPI_PROT_SDR); in f_ospi_config_indir_protocol()
284 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ADDR, OSPI_PROT_SDR); in f_ospi_config_indir_protocol()
285 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_CODE, OSPI_PROT_SDR); in f_ospi_config_indir_protocol()
309 prot |= FIELD_PREP(OSPI_PROT_DATA_UNIT_MASK, unit); in f_ospi_config_indir_protocol()
[all …]
/u-boot/drivers/i2c/
A Docteon_i2c.c311 FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA); in twsi_write_ctl()
326 FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA); in twsi_read_ctl()
344 FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA); in twsi_read_status()
466 FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_DATA) | in twsi_write_data()
467 FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA); in twsi_write_data()
489 FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_DATA) | in twsi_write_data()
490 FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA); in twsi_write_data()
564 FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_DATA) | in twsi_read_data()
565 FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA); in twsi_read_data()
663 FIELD_PREP(TWSI_SW_EOP_IA_MASK, 0) | in twsi_init()
[all …]
/u-boot/drivers/rtc/
A Dmax313xx.c289 regs[5] |= FIELD_PREP(MAX313XX_MONTH_CENTURY, 1); in max313xx_set_time()
390 reg = FIELD_PREP(MAX31329_TRICKLE_ENABLE_BIT, 1) | in max313xx_trickle_charger_setup()
391 FIELD_PREP(MAX31329_43_TRICKLE_RES_MASK, index) | in max313xx_trickle_charger_setup()
392 FIELD_PREP(MAX31329_43_TRICKLE_DIODE_EN, diode); in max313xx_trickle_charger_setup()
396 reg = FIELD_PREP(MAX3133X_TRICKLE_ENABLE_BIT, 1) | in max313xx_trickle_charger_setup()
397 FIELD_PREP(MAX3133X_TRICKLE_DIODE_EN, diode) | in max313xx_trickle_charger_setup()
398 FIELD_PREP(MAX3133X_TRICKLE_RES_MASK, index); in max313xx_trickle_charger_setup()
403 reg = FIELD_PREP(MAX31341_TRICKLE_ENABLE_BIT, 1) | in max313xx_trickle_charger_setup()
404 FIELD_PREP(MAX31341_TRICKLE_DIODE_EN, diode) | in max313xx_trickle_charger_setup()
405 FIELD_PREP(MAX31341_TRICKLE_RES_MASK, index); in max313xx_trickle_charger_setup()
[all …]
/u-boot/drivers/usb/host/
A Ddwc3-octeon-glue.c103 gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL, in dwc3_octeon_config_power()
110 gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL, in dwc3_octeon_config_power()
119 gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL, in dwc3_octeon_config_power()
232 uctl_ctl |= FIELD_PREP(UCTL_CTL_H_CLKDIV_SEL, div); in dwc3_octeon_clocks_start()
250 uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_SEL, ref_clk_sel); in dwc3_octeon_clocks_start()
252 uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_FSEL, 0x07); in dwc3_octeon_clocks_start()
264 uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_FSEL, 0x27); in dwc3_octeon_clocks_start()
275 uctl_ctl |= FIELD_PREP(UCTL_CTL_MPLL_MULTIPLIER, mpll_mul); in dwc3_octeon_clocks_start()
334 shim_cfg |= FIELD_PREP(UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1); in dwc3_octeon_set_endian_mode()
336 shim_cfg |= FIELD_PREP(UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1); in dwc3_octeon_set_endian_mode()
/u-boot/drivers/pwm/
A Dpwm-aspeed.c97 FIELD_PREP(PWM_ASPEED_CTRL_INVERSE, in aspeed_pwm_set_invert()
174 FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD, in aspeed_pwm_set_config()
176 FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, in aspeed_pwm_set_config()
184 FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) | in aspeed_pwm_set_config()
185 FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) | in aspeed_pwm_set_config()
186 FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en)); in aspeed_pwm_set_config()
/u-boot/drivers/mtd/nand/raw/
A Dmt7621_nand.c161 (FIELD_PREP(ACCCON_POECS, tpoecs) | \
162 FIELD_PREP(ACCCON_PRECS, tprecs) | \
163 FIELD_PREP(ACCCON_C2R, tc2r) | \
164 FIELD_PREP(ACCCON_W2R, tw2r) | \
165 FIELD_PREP(ACCCON_WH, twh) | \
166 FIELD_PREP(ACCCON_WST, twst) | \
167 FIELD_PREP(ACCCON_RLT, trlt))
702 FIELD_PREP(DEC_CS, decode_block_size) | in mt7621_nfc_ecc_init()
735 pagefmt = FIELD_PREP(PAGEFMT_PAGE, i) | in mt7621_nfc_set_page_format()
736 FIELD_PREP(PAGEFMT_SPARE, spare_size) | in mt7621_nfc_set_page_format()
[all …]
/u-boot/drivers/net/phy/
A Dintel_xway.c21 val |= FIELD_PREP(XWAY_MDIO_MIICTRL_TXSKEW_MASK, rx_delay / 500); in xway_config()
22 val |= FIELD_PREP(XWAY_MDIO_MIICTRL_RXSKEW_MASK, tx_delay / 500); in xway_config()
/u-boot/drivers/misc/
A Dnpcm_host_intf.c34 #define IOMODE_SDQ FIELD_PREP(IOMODE_MASK, 3)
36 #define MAXFREQ_33MHZ FIELD_PREP(MAXFREQ_MASK, 2)
88 val |= IOMODE_SDQ | MAXFREQ_33MHZ | FIELD_PREP(CHSUPP_MASK, ch_supp); in npcm_host_intf_bind()
/u-boot/arch/arm/mach-uniphier/clk/
A Dpll-base-ld20.c41 tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK, in uniphier_ld20_sscpll_init()
48 tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK, in uniphier_ld20_sscpll_init()
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
/u-boot/arch/mips/mach-mtmips/mt7621/spl/
A Dcps.c65 FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG0_MASK_VALUE) | in cm_init()
70 FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG1_MASK_VALUE) | in cm_init()
75 FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG2_MASK_VALUE) | in cm_init()
80 FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG3_MASK_VALUE) | in cm_init()
/u-boot/drivers/adc/
A Dmeson-saradc.c369 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0); in meson_saradc_enable_channel()
374 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), channel); in meson_saradc_enable_channel()
378 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, in meson_saradc_enable_channel()
384 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, in meson_saradc_enable_channel()
541 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, in meson_saradc_init()
545 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, in meson_saradc_init()
551 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, in meson_saradc_init()
555 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, in meson_saradc_init()
562 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0); in meson_saradc_init()
566 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1); in meson_saradc_init()
[all …]
/u-boot/drivers/watchdog/
A Docteontx_wdt.c64 val = FIELD_PREP(WDOG_MODE, 0x3) | in octeontx_wdt_start()
65 FIELD_PREP(WDOG_LEN, tout_wdog) | in octeontx_wdt_start()
66 FIELD_PREP(WDOG_CNT, tout_wdog << 8); in octeontx_wdt_start()

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