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Searched refs:FSL_DDR_CS0_CS1_CS2_CS3 (Results 1 – 5 of 5) sorted by relevance

/u-boot/drivers/ddr/fsl/
A Doptions.c726 return FSL_DDR_CS0_CS1_CS2_CS3; in auto_bank_intlv()
732 return FSL_DDR_CS0_CS1_CS2_CS3; in auto_bank_intlv()
736 return FSL_DDR_CS0_CS1_CS2_CS3; in auto_bank_intlv()
1212 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; in populate_memctl_options()
1218 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in populate_memctl_options()
1219 case FSL_DDR_CS0_CS1_CS2_CS3: in populate_memctl_options()
A Dutil.c312 case FSL_DDR_CS0_CS1_CS2_CS3: in print_ddr_info()
A Dmain.c392 FSL_DDR_CS0_CS1_CS2_CS3) { in __step_assign_addresses()
393 case FSL_DDR_CS0_CS1_CS2_CS3: in __step_assign_addresses()
A Dctrl_regs.c2386 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in compute_fsl_memctl_config_regs()
2387 case FSL_DDR_CS0_CS1_CS2_CS3: in compute_fsl_memctl_config_regs()
2412 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in compute_fsl_memctl_config_regs()
2413 case FSL_DDR_CS0_CS1_CS2_CS3: in compute_fsl_memctl_config_regs()
/u-boot/include/
A Dfsl_ddr_sdram.h86 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) macro

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