| /u-boot/arch/arm/cpu/armv7/sunxi/ |
| A D | psci.c | 28 #define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15) macro
225 reg = readl(GICC_BASE + GICC_IAR); in psci_fiq_enter()
232 writel(reg, GICC_BASE + GICC_EOIR); in psci_fiq_enter()
304 writel(0xff, GICC_BASE + GICC_PMR); in psci_arch_init()
307 setbits_le32(GICC_BASE + GICC_CTLR, BIT(3)); in psci_arch_init()
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| /u-boot/arch/arm/mach-socfpga/ |
| A D | lowlevel_init_soc64.S | 35 ldr x1, =GICC_BASE
50 ldr x0, =GICC_BASE
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| /u-boot/include/configs/ |
| A D | meson64.h | 13 #define GICC_BASE 0xffc02000 macro
16 #define GICC_BASE 0xc4302000 macro
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| A D | px30_common.h | 14 #define GICC_BASE 0xff132000 macro
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| A D | rcar-gen3-common.h | 18 #define GICC_BASE 0xF1020000 macro
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| A D | rv1126_common.h | 17 #define GICC_BASE 0xfeff2000 macro
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| A D | hikey960.h | 25 #define GICC_BASE 0xe82b2000 macro
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| A D | hikey.h | 31 #define GICC_BASE 0xf6802000 macro
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| A D | presidio_asic.h | 19 #define GICC_BASE 0xf7012000 macro
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| A D | vexpress_aemv8.h | 80 #define GICC_BASE (0x2C02f000) macro
83 #define GICC_BASE (V2M_PA_BASE + 0x2c000000) macro
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| A D | xilinx_zynqmp.h | 15 #define GICC_BASE 0xF9020000 macro
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| /u-boot/board/cortina/presidio-asic/ |
| A D | lowlevel_init.S | 45 ldr x1, =GICC_BASE
60 ldr x0, =GICC_BASE
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| /u-boot/arch/arm/mach-rmobile/ |
| A D | lowlevel_init_gen3.S | 62 ldr x1, =GICC_BASE
76 ldr x0, =GICC_BASE
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| /u-boot/arch/arm/include/asm/arch-tegra186/ |
| A D | tegra.h | 10 #define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */ macro
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| /u-boot/arch/arm/include/asm/arch-fsl-layerscape/ |
| A D | config.h | 224 #define GICC_BASE 0x01402000 macro
250 #define GICC_BASE 0x01402000 macro
266 #define GICC_BASE 0x01420000 macro
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| /u-boot/arch/arm/include/asm/arch-tegra210/ |
| A D | tegra.h | 11 #define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ macro
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| /u-boot/arch/arm/mach-snapdragon/include/mach/ |
| A D | sysmap-apq8016.h | 11 #define GICC_BASE (0x0b002000) macro
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| A D | sysmap-qcs404.h | 11 #define GICC_BASE (0x0b002000) macro
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| /u-boot/arch/arm/mach-socfpga/include/mach/ |
| A D | base_addr_soc64.h | 46 #define GICC_BASE 0xfffc2000 macro
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| /u-boot/arch/arm/cpu/armv8/ |
| A D | start.S | 302 ldr x1, =GICC_BASE
317 ldr x0, =GICC_BASE
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| /u-boot/arch/arm/lib/ |
| A D | gic_64.S | 57 ldr x1, =GICC_BASE /* GICC_CTLR */
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| /u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| A D | lowlevel.S | 36 ldr x1, =GICC_BASE
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| A D | fdt.c | 210 reg[2] = cpu_to_fdt64(GICC_BASE); in fdt_fixup_gic()
|