Searched refs:GMII (Results 1 – 4 of 4) sorted by relevance
| /u-boot/arch/mips/mach-octeon/ |
| A D | cvmx-helper-util.c | 74 { GMII, 0x800, 0x8ff, 0x40 }, /* Interface 0 */
75 { GMII, 0x900, 0x9ff, 0x40 }, /* Interface 1 */
76 { GMII, 0xa00, 0xaff, 0x40 }, /* Interface 2 */
77 { GMII, 0xb00, 0xbff, 0x40 }, /* Interface 3 */
78 { GMII, 0xc00, 0xcff, 0x40 }, /* Interface 4 */
94 { GMII, 0x800, 0x83f, 0x00 }, /* Interface 0 - BGX0 */
95 { GMII, 0x900, 0x93f, 0x00 }, /* Interface 1 -BGX1 */
96 { GMII, 0xa00, 0xa3f, 0x00 }, /* Interface 2 -BGX2 */
97 { GMII, 0xb00, 0xb3f, 0x00 }, /* Interface 3 - BGX3 */
732 if (port_map[xi.interface].type == GMII) { in cvmx_helper_get_ipd_port()
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| /u-boot/drivers/net/phy/ |
| A D | Kconfig | 329 bool "Xilinx GMII to RGMII Ethernet PHYs support"
331 This adds support for Xilinx GMII to RGMII IP core. This IP acts
332 as bridge between MAC connected over GMII and external phy that
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| /u-boot/doc/device-tree-bindings/net/ |
| A D | snps,dwc-qos-ethernet.txt | 26 In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
31 In some configurations (e.g. GMII/RGMII), this clock is derived from the
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| /u-boot/arch/arm/dts/ |
| A D | sun6i-a31.dtsi | 633 * data lines in GMII mode run at 125MHz and
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