Home
last modified time | relevance | path

Searched refs:GPC_BASE_ADDR (Results 1 – 9 of 9) sorted by relevance

/u-boot/arch/arm/mach-imx/imx8m/
A Dpsci.c96 clrbits_le32((void *)GPC_BASE_ADDR + GPC_LPCR_A53_AD, EN_Cn_WFI_PDN(cpu)); in psci_cpu_on_power_on()
98 setbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR); in psci_cpu_on_power_on()
99 setbits_le32((void *)GPC_BASE_ADDR + GPC_CPU_PGC_SW_PUP_REQ, COREn_A53_SW_PUP_REQ(cpu)); in psci_cpu_on_power_on()
102 while (readl(GPC_BASE_ADDR + GPC_CPU_PGC_SW_PUP_REQ) & COREn_A53_SW_PUP_REQ(cpu)) in psci_cpu_on_power_on()
105 clrbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR); in psci_cpu_on_power_on()
115 setbits_le32((void *)GPC_BASE_ADDR + GPC_LPCR_A53_AD, EN_Cn_WFI_PDN(cpu)); in psci_cpu_on_power_off()
116 setbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR); in psci_cpu_on_power_off()
A Dsoc.c615 struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840); in arch_cpu_init()
616 struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880); in arch_cpu_init()
617 struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0); in arch_cpu_init()
618 struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR; in arch_cpu_init()
A Dclock_imx8mm.c91 setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); in fracpll_configure()
92 setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); in fracpll_configure()
/u-boot/board/softing/vining_2000/
A Dvining_2000.c421 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR; in board_preboot_os()
/u-boot/arch/arm/include/asm/arch-mx5/
A Dimx-regs.h78 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) macro
/u-boot/drivers/pci/
A Dpcie_imx.c460 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR; in imx6_pcie_assert_core_reset()
/u-boot/arch/arm/include/asm/arch-vf610/
A Dimx-regs.h83 #define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) macro
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dimx-regs.h33 #define GPC_BASE_ADDR 0x303A0000 macro
/u-boot/arch/arm/include/asm/arch-mx6/
A Dimx-regs.h201 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) macro

Completed in 36 milliseconds