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/u-boot/arch/arm/dts/
A Dsynquacer-sc2a11-developerbox.dts39 "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B",
40 "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT",
41 "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F",
42 "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J",
43 "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27",
A Dhi3798cv200-poplar.dts116 gpio-line-names = "GPIO-E", "",
118 "", "GPIO-F",
119 "", "GPIO-J";
124 gpio-line-names = "GPIO-H", "GPIO-I",
125 "GPIO-L", "GPIO-G",
126 "GPIO-K", "",
134 "GPIO-C", "",
135 "", "GPIO-B";
142 "", "GPIO-D",
150 "", "GPIO-A",
A Dimx8mp-dhcom-pdk2.dts30 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */
31 label = "TA1-GPIO-A";
39 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */
40 label = "TA2-GPIO-B";
48 gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
49 label = "TA3-GPIO-C";
57 gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */
58 label = "TA4-GPIO-D";
73 gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */
82 gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */
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A Dimx6qdl-dhcom-pdk2.dtsi63 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */
64 label = "TA1-GPIO-A";
72 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */
73 label = "TA2-GPIO-B";
81 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */
82 label = "TA3-GPIO-C";
90 gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */
91 label = "TA4-GPIO-D";
103 * Disable led-5, because GPIO E is
110 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
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A Dimx6qdl-dhcom-drc02.dtsi26 * GPIO line, however the i.MX6 UART driver assumes RX happens
32 gpios = <18 0>; /* GPIO Q */
74 * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts.
77 cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */
80 rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
86 * controlled by DHCOM GPIO P. So remove rts/cts pins and the property
87 * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via
88 * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1
95 rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */
A Dhi3660-hikey960.dts79 label = "GPIO Power";
202 * Legend: proper name = the GPIO line is used as GPIO
224 * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
225 * ones actually used for GPIO.
256 "GPIO-J", /* LSEC pin 32: GPIO_019 */
258 "GPIO-L", /* LSEC pin 34: GPIO_021 */
260 "GPIO-G"; /* LSEC pin 29: LCD_TE0 */
265 /* The rail from pin BK36 is named LCD_TE0, we assume to be muxed as GPIO for GPIO-G */
491 "GPIO-A", /* LSEC pin 23: GPIO_208 */
492 "GPIO-B", /* LSEC pin 24: GPIO_209 */
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A Dimx8mp-dhcom-pdk3.dts69 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */
70 label = "TA1-GPIO-A";
78 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */
79 label = "TA2-GPIO-B";
87 gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
88 label = "TA3-GPIO-C";
96 gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; /* GPIO E */
97 label = "TA4-GPIO-E";
113 gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; /* GPIO D */
133 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* GPIO G */
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A Dsocfpga_cyclone5_mcvevk.dts35 &gpio0 { /* GPIO 0 ... 28 */
39 &gpio1 { /* GPIO 29 ... 57 */
43 &gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
58 irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */
/u-boot/drivers/gpio/
A DKconfig2 # GPIO infrastructure and drivers
5 menuconfig GPIO config
6 bool "GPIO support"
17 if GPIO
23 Enable driver model for GPIO access. The standard GPIO
34 Enable driver model for GPIO access in SPL. The standard GPIO
45 Enable driver model for GPIO access in TPL. The standard GPIO
56 Enable driver model for GPIO access in VPL. The standard GPIO
67 The GPIO chip may contain GPIO hog definitions. GPIO hogging
76 The GPIO chip may contain GPIO hog definitions. GPIO hogging
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/u-boot/doc/device-tree-bindings/sysinfo/
A Dgpio-sysinfo.txt1 GPIO-based Sysinfo device
3 This binding describes several GPIOs which specify a board revision. Each GPIO
7 Each GPIO may be floating, pulled-up, or pulled-down, mapping to digits 2, 1,
8 and 0, respectively. The first GPIO forms the least-significant digit of the
13 If GPIO 0 is pulled-up, GPIO 1 is pulled-down, and GPIO 2 is floating, then the
18 If instead GPIO 0 is floating, GPIO 1 is pulled-up, and GPIO 2 is pulled-down,
/u-boot/arch/x86/include/asm/arch-apollolake/acpi/
A Dgpiolib.asl11 /* Arg0 - GPIO DW0 address */
23 /* Arg0 - GPIO DW0 address */
36 /* Arg0 - GPIO DW0 address */
48 /* Arg0 - GPIO DW0 address */
61 /* Arg0 - GPIO portid */
62 /* Arg1 - GPIO pad offset relative to the community */
74 /* Arg0 - GPIO pad offset relative to the community */
79 /* Get Host ownership register of GPIO Community */
82 /* Arg0 - GPIO portid */
94 /* Set Host ownership register of GPIO Community */
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/u-boot/drivers/pinctrl/
A Dpinctrl-k210.c196 DEFAULT(GPIO),
246 FUNC(GPIOHS0, GPIO),
247 FUNC(GPIOHS1, GPIO),
248 FUNC(GPIOHS2, GPIO),
249 FUNC(GPIOHS3, GPIO),
250 FUNC(GPIOHS4, GPIO),
251 FUNC(GPIOHS5, GPIO),
252 FUNC(GPIOHS6, GPIO),
253 FUNC(GPIOHS7, GPIO),
254 FUNC(GPIOHS8, GPIO),
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/u-boot/doc/device-tree-bindings/gpio/
A Dgpio.txt1 Specifying GPIO information for devices
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
57 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
83 1.1) GPIO specifier best practices
124 responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
134 Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
185 The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
189 Each GPIO hog definition is represented as a child node of the GPIO controller.
192 - gpios: Store the GPIO information (id, flags, ...) for each GPIO to
243 The GPIO controller offset pertains to the GPIO controller node containing the
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A Dnvidia,tegra186-gpio.txt1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
75 - "gpio": Mandatory. GPIO control registers. This may cover either:
96 Marks the device node as a GPIO controller/provider.
100 Indicates how many cells are used in a consumer's GPIO specifier.
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A Dmscc_sgpio.txt1 Microsemi Corporation (MSCC) Serial GPIO driver
3 The MSCC serial GPIO extends the number or GPIO's on the system by
6 effective GPIO count can be extended by up to 128 GPIO's per
17 - gpio-controller : Marks the device node as a GPIO controller.
31 regular GPIO pins.
A Dsnps,creg-gpio.txt1 GPIO via CREG (control registers) driver
15 - gpio-controller : Marks the device node as a GPIO controller.
16 - gpio-count: Number of GPIO pins.
18 - gpio-first-shift: Shift (in bits) of the first GPIO field in register
21 output to "1" (see picture). Applied to all GPIO ports.
23 output to "0" (see picture). Applied to all GPIO ports.
/u-boot/arch/x86/include/asm/
A Dintel_pinctrl_defs.h228 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
236 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
241 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
248 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
255 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
266 PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \
273 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
280 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
301 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
308 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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/u-boot/board/firefly/roc-pc-rk3399/
A Droc-pc-rk3399.c65 spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1); in led_setup()
67 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5), in led_setup()
72 spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0); in led_setup()
75 spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); in led_setup()
/u-boot/doc/device-tree-bindings/pinctrl/
A Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and GPIO controller
3 Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
6 GPIO and pin controller:
21 - reg: The first set of registers is for pinctrl/GPIO and the second
23 - interrupts: list of interrupts used by the GPIO
141 GPIO subnode:
144 and the common GPIO bindings used by client devices.
146 Required properties for the GPIO driver under the gpio subnode:
148 - gpio-controller: Marks the device node as a GPIO controller.
150 second cell specifies GPIO flags, as defined in
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/u-boot/doc/device-tree-bindings/spi/
A Dsoft-spi.txt3 The soft SPI bus implementation allows the use of GPIO pins to simulate a
12 gpio-sck: GPIO to use for SPI clock (output)
14 gpio-mosi: GPIO to use for SPI MOSI line (output)
15 gpio-miso: GPIO to use for SPI MISO line (input)
20 The GPIOs should be specified as required by the GPIO controller referenced.
22 typically holds the GPIO number.
/u-boot/arch/x86/include/asm/arch-tangier/acpi/
A Dsouthcluster.asl33 /* GPIO Low Memory Region */
105 GPIO
134 GPIO
148 If (^^GPIO.AVBL == One)
150 ^^GPIO.WFD3 = One
162 GPIO
174 If (^^^GPIO.AVBL == One)
176 ^^^GPIO.WFD3 = Zero
187 ^^^GPIO.WFD3 = One
307 Device (GPIO)
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/u-boot/arch/powerpc/cpu/mpc83xx/sysio/
A DKconfig.mpc830875 bool "GPIO"
89 bool "GPIO"
103 bool "GPIO"
108 prompt "GPIO A group"
111 bool "GPIO"
119 prompt "GPIO B group"
122 bool "GPIO"
139 bool "GPIO"
158 bool "GPIO"
166 bool "GPIO"
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/u-boot/drivers/pinctrl/nuvoton/
A DKconfig3 bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX"
6 Say Y here to enable pin controller and GPIO support
16 The NPCM8XX contains 256 GPIO pins. Most of them are
18 be configured as either GPIO pin or alternate function.
/u-boot/doc/usage/cmd/
A Dgpio.rst20 Switch the GPIO *pin* to input mode.
25 Switch the GPIO *pin* to output mode and set the signal to 1.
30 Switch the GPIO *pin* to output mode and set the signal to 0.
35 Switch the GPIO *pin* to output mode and reverse the signal state.
40 Read the signal state of the GPIO *pin* and save it in environment variable
81 Name of a single GPIO to be displayed or manipulated.
86 Switch the status of a GPIO::
105 Show the GPIO status::
/u-boot/board/intel/cherryhill/
A Dcherryhill.c29 GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
32 GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
35 GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
38 GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
41 GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
44 GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
47 GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
50 GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW,
53 GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW,
56 GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW,
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