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Searched refs:HIT_INVALIDATE_I (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/mips/include/asm/
A Dcacheops.h55 #define HIT_INVALIDATE_I 0x00 macro
57 #define HIT_INVALIDATE_I 0x10 macro
/u-boot/arch/mips/lib/
A Dcache.c125 HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I); in flush_cache()
136 cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); in flush_cache()

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