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Searched refs:I2C1_BASE_ADDR (Results 1 – 15 of 15) sorted by relevance

/u-boot/arch/arm/include/asm/arch-stv0991/
A Dhardware.h50 #define I2C1_BASE_ADDR 0x80401000UL macro
/u-boot/arch/arm/include/asm/arch-ls102xa/
A Dconfig.h42 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) macro
/u-boot/arch/arm/mach-imx/
A Di2c-mxv7.c65 (void *)I2C1_BASE_ADDR,
/u-boot/arch/arm/mach-imx/mx6/
A Dmodule_fuse.c295 case I2C1_BASE_ADDR: in i2c_fused()
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dsoc.c347 #ifdef I2C1_BASE_ADDR in erratum_a009203()
348 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); in erratum_a009203()
/u-boot/drivers/i2c/
A Dmxc_i2c.c351 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
360 { 0, I2C1_BASE_ADDR, 0 },
/u-boot/arch/arm/include/asm/arch-mx5/
A Dimx-regs.h109 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) macro
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
A Dimmap_lsch3.h56 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) macro
A Dimmap_lsch2.h67 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) macro
/u-boot/arch/arm/include/asm/arch-mx27/
A Dimx-regs.h186 #define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE) macro
/u-boot/arch/arm/include/asm/arch-vf610/
A Dimx-regs.h77 #define I2C1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) macro
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dimx-regs.h43 #define I2C1_BASE_ADDR 0x30A20000 macro
/u-boot/arch/arm/include/asm/arch-mx31/
A Dimx-regs.h613 #define I2C1_BASE_ADDR 0x43f80000 macro
/u-boot/arch/arm/include/asm/arch-mx6/
A Dimx-regs.h262 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) macro
/u-boot/arch/arm/include/asm/arch-mx7/
A Dimx-regs.h173 #define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000) macro

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