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/u-boot/doc/
A DREADME.bitbangMII16 MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional)
17 MDIO_ACTIVE - Activate the MDIO pin as out pin
18 MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
19 MDIO_READ - Read the MDIO pin
20 MDIO(v) - Write v on the MDIO pin
37 int (*mdio_active)() - Activate the MDIO pin as output
38 int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
39 int (*set_mdio)() - Write the MDIO pin
40 int (*get_mdio)() - Read the MDIO pin
/u-boot/doc/device-tree-bindings/net/
A Dmarvell-mdio.txt1 * Marvell MDIO Ethernet Controller interface
4 have an identical unit that provides an interface with the MDIO bus.
5 This driver handles this MDIO interface.
15 Please refer to "mdio.txt" for generic MDIO bus bindings.
A Dmdio.txt1 Common MDIO bus properties.
3 These are generic properties that can apply to any MDIO bus.
6 - device-name - If present it is used to name the device and MDIO bus.
14 This example shows the structure used for the external MDIO bus on NXP LS1028A
15 RDB board. Note that this MDIO device is an integrated PCI function and
A Dmdio-mux.txt1 The expected structure of an MDIO MUX device tree node is described here. This
4 by U-Boot, not optional as is in Linux. Current U-Boot MDIO MUX udevice class
8 The MDIO buses downstream of the MUX should be described in the device tree as
12 mdio-parent-bus = a phandle to the MDIO bus used to perform actual I/O. This is
13 typically a real MDIO device, unless there are cascaded MUXes.
14 #address-cells = <1>, each MDIO group is identified by one 32b value.
18 The properties described here are sufficient for MDIO MUX DM class code, but
23 MDIO.
30 /* The parent MDIO bus. */
A Dfsl-tsec-phy.txt39 connected via the MDIO bus (sometimes the MDIO bus controller is separate).
41 * MDIO IO device
43 The MDIO is a bus to which the PHY devices are connected. For each
62 * TBI Internal MDIO bus
65 This PHY is accessed through the local MDIO bus. These buses are defined
A Dmdio-mux-reg.txt1 Device tree structures used by register based MDIO muxes is described here.
36 /* on-board MDIO with a single RGMII PHY */
79 /* Parent MDIO, defined in SoC .dtsi file, just enabled here */
A Dethernet.txt70 "auto", "in-band-status". "auto" is the default, it usess MDIO for
74 connected via the MDIO bus (sometimes the MDIO bus controller is separate).
76 For non-MDIO PHY management see fixed-link.txt.
A Dallwinner,sun4i-mdio.txt1 * Allwinner A10 MDIO Ethernet Controller interface
A Dphy.txt5 a MDIO bus and the bus is used to access the PHY.
A Dfixed-link.txt5 normal MDIO-managed PHY device. For those situations, a Device Tree
/u-boot/arch/powerpc/dts/
A Dkmeter1.dts90 0 1 3 0 2 0 /* MDIO */
114 0 1 3 0 2 0 /* MDIO */
138 0 1 3 0 2 0 /* MDIO */
156 0 1 3 0 2 0 /* MDIO */
172 0 1 3 0 2 0 /* MDIO */
188 0 1 3 0 2 0 /* MDIO */
204 0 1 3 0 2 0 /* MDIO */
339 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
355 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
371 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
[all …]
A Dkmcoge5ne.dts97 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
119 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
137 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
221 /* mng-switch port (UCC1, MDIO 0x10, RGMII) */
238 /* admin and debug port (UCC4, MDIO 0x00, RMII) */
254 /* mate backplane port (UCC5, MDIO 0x08, RMII) */
276 /* admin front port (UCC4, MDIO 0x00, RMII) */
281 /* mate bp port (UCC5, MDIO 0x08, RMII) */
A Dkmtuge1.dts41 3 4 3 0 2 0 /* MDIO */
A Dkmtuxa1.dts41 3 4 3 0 2 0 /* MDIO */
A Dkm8321.dtsi153 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
175 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
A Dkmsupm5.dts76 3 4 3 0 2 0 /* MDIO */
A Dkmsupc5.dts76 3 4 3 0 2 0 /* MDIO */
A Dkmtepr2.dts82 3 4 3 0 2 0 /* MDIO */
/u-boot/arch/arm/dts/
A Dam335x-draco.dts92 /* MDIO */
100 /* MDIO reset value */
108 /* MDIO via GPIO */
128 gpios = <&gpio0 1 GPIO_ACTIVE_HIGH /* MDIO-CLK */
129 &gpio0 0 GPIO_ACTIVE_HIGH>; /* MDIO-DATA */
A Dfsl-ls1088a-u-boot.dtsi20 /* MDIO controllers - U-Boot uses a different
A Darmada-38x-controlcenterdc.dts245 /*MDIO*/ &gpio0 14 0>;
349 /*MDIO*/ &gpio1 13 0>;
453 /*MDIO*/ &gpio0 24 0>;
A Dzynq-dlc20-rev1.0.dts47 status = "okay"; /* MIO16-MIO27, MDIO MIO52/53 */
A Dk3-am642-evm-u-boot.dtsi116 pinctrl-0 = <&mdio1_pins_default /* HACK: as MDIO driver is not DM enabled */
/u-boot/drivers/net/
A DKconfig23 bool "Enable Driver Model for MDIO devices"
26 Enable driver model for MDIO devices
36 bool "Enable Driver Model for MDIO MUX devices"
39 Enable driver model for MDIO MUX devices
43 the MDIO bus.
65 bool "Sandbox: Mocked MDIO driver"
75 bool "Sandbox: Mocked MDIO-MUX driver"
78 the MDIO bux. It uses mdio_sandbox driver as parent MDIO.
367 two FEC controllers share MDIO bus.
920 bool "Marvell MDIO interface support"
[all …]
/u-boot/include/dt-bindings/clock/
A Dstm32mp1-clks.h44 #define MDIO 31 macro

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