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Searched refs:MPLL_CON1_VAL (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/arm/mach-exynos/
A Dclock_init_exynos4.c86 writel(MPLL_CON1_VAL, &clk->mpll_con1); in system_clock_init()
A Dexynos5_setup.h446 #define MPLL_CON1_VAL (0x00203800) macro
711 #define MPLL_CON1_VAL (0x0020F300) macro
A Dexynos4_setup.h352 #define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0)) macro
A Dclock_init_exynos5.c626 writel(MPLL_CON1_VAL, &clk->mpll_con1); in exynos5250_system_clock_init()
847 writel(MPLL_CON1_VAL, &clk->mpll_con1); in exynos5420_system_clock_init()
/u-boot/board/samsung/trats/
A Dtrats.c343 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1); in board_clock_init()
A Dsetup.h254 #define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0)) macro

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