Searched refs:NPLL (Results 1 – 8 of 8) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | xlnx-versal-clk.h | 23 #define NPLL 14 macro
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | cru_rk3368.h | 20 NPLL, enumerator
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| A D | cru_px30.h | 27 NPLL, enumerator
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| A D | cru_rk3568.h | 25 NPLL, enumerator
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| A D | cru_rk3588.h | 28 NPLL, enumerator
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_px30.c | 788 parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL); in px30_vop_get_clk()
832 npll_hz = px30_clk_get_pll_rate(priv, NPLL); in px30_vop_set_clk()
847 rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL, in px30_vop_set_clk()
1093 pll_rate = px30_clk_get_pll_rate(priv, NPLL); in px30_mac_set_clk()
1209 rate = px30_clk_get_pll_rate(priv, NPLL); in px30_clk_get_rate()
1292 ret = px30_clk_set_pll_rate(priv, NPLL, rate); in px30_clk_set_rate()
1441 npll_hz = px30_clk_get_pll_rate(priv, NPLL); in px30_clk_init()
1443 ret = px30_clk_set_pll_rate(priv, NPLL, NPLL_HZ); in px30_clk_init()
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| A D | clk_rk3588.c | 64 [NPLL] = PLL(pll_rk3588, PLL_NPLL, RK3588_PLL_CON(120),
1495 rate = rockchip_pll_get_rate(&rk3588_pll_clks[NPLL], priv->cru, in rk3588_clk_get_rate()
1496 NPLL); in rk3588_clk_get_rate()
1654 ret = rockchip_pll_set_rate(&rk3588_pll_clks[NPLL], priv->cru, in rk3588_clk_set_rate()
1655 NPLL, rate); in rk3588_clk_set_rate()
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| A D | clk_rk3568.c | 86 [NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3568_PLL_CON(32),
2350 rate = rockchip_pll_get_rate(&rk3568_pll_clks[NPLL], priv->cru, in rk3568_clk_get_rate()
2351 NPLL); in rk3568_clk_get_rate()
2530 ret = rockchip_pll_set_rate(&rk3568_pll_clks[NPLL], priv->cru, in rk3568_clk_set_rate()
2531 NPLL, rate); in rk3568_clk_set_rate()
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Completed in 28 milliseconds