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Searched refs:OFFSET (Results 1 – 25 of 34) sorted by relevance

12

/u-boot/board/siemens/rut/
A Dmux.c28 {OFFSET(ddr_resetn), (MODE(0))},
30 {OFFSET(ddr_ck), (MODE(0))},
31 {OFFSET(ddr_nck), (MODE(0))},
54 {OFFSET(ddr_odt), (MODE(0))},
83 {OFFSET(gpmc_ad8), (MODE(1))},
84 {OFFSET(gpmc_ad9), (MODE(1))},
85 {OFFSET(gpmc_ad10), (MODE(1))},
86 {OFFSET(gpmc_ad11), (MODE(1))},
87 {OFFSET(gpmc_ad12), (MODE(1))},
88 {OFFSET(gpmc_ad13), (MODE(1))},
[all …]
/u-boot/board/siemens/draco/
A Dmux.c34 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
36 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
65 {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */
229 {OFFSET(mii1_col), (MODE(3) | RXACTIVE)},
230 {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
232 {OFFSET(mii1_txen), (MODE(1))},
233 {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)},
234 {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
236 {OFFSET(mii1_txd1), (MODE(1))},
237 {OFFSET(mii1_txd0), (MODE(1))},
[all …]
/u-boot/board/bosch/shc/
A Dmux.c109 {OFFSET(tdo), (MODE(0) | PULLUP_EN)},
111 {OFFSET(ntrst), (MODE(0) | RXACTIVE)},
115 {OFFSET(rsvd2), (MODE(0) | PULLUP_EN)},
177 {OFFSET(mii1_col), MODE(0) | RXACTIVE},
178 {OFFSET(mii1_crs), MODE(0) | RXACTIVE},
180 {OFFSET(mii1_txen), MODE(0)},
181 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},
182 {OFFSET(mii1_txd3), MODE(0)},
183 {OFFSET(mii1_txd2), MODE(0)},
184 {OFFSET(mii1_txd1), MODE(0) | RXACTIVE},
[all …]
/u-boot/board/siemens/pxm2/
A Dmux.c68 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
69 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
84 {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
86 {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
87 {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
88 {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
89 {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
90 {OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */
93 {OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */
142 {OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */
[all …]
/u-boot/board/BuR/brsmarc1/
A Dmux.c21 {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
23 {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
25 {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
51 {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
59 {OFFSET(uart0_rtsn), MODE(2) | RXACTIVE},
121 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
129 {OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},
134 {OFFSET(mmc0_dat0), (MODE(3) | PULLUDEN)},
136 {OFFSET(mmc0_cmd), (MODE(2) | PULLUDEN)},
143 {OFFSET(mii1_txd2), (MODE(3) | PULLUDEN)},
[all …]
/u-boot/board/BuR/brppt1/
A Dmux.c20 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
38 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
83 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
85 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
86 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
101 {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
103 {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
104 {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
105 {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
[all …]
/u-boot/board/BuR/brxre1/
A Dmux.c20 {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
22 {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
24 {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
36 {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
44 {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
56 {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
62 {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
64 {OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
70 {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
72 {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
[all …]
/u-boot/board/ti/am335x/
A Dmux.c112 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
114 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
120 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
122 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
128 {OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE |
130 {OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE |
137 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
140 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
175 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
177 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
[all …]
/u-boot/board/ti/am43xx/
A Dmux.c15 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
16 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
17 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
18 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
19 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
28 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
30 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
31 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
32 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
33 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
[all …]
/u-boot/board/compulab/cm_t43/
A Dmux.c12 {OFFSET(mii1_txen), MODE(2)},
13 {OFFSET(mii1_txd3), MODE(2)},
14 {OFFSET(mii1_txd2), MODE(2)},
15 {OFFSET(mii1_txd1), MODE(2)},
16 {OFFSET(mii1_txd0), MODE(2)},
17 {OFFSET(mii1_txclk), MODE(2)},
28 {OFFSET(gpmc_a0), MODE(2)}, /* txen */
29 {OFFSET(gpmc_a2), MODE(2)}, /* txd3 */
30 {OFFSET(gpmc_a3), MODE(2)}, /* txd2 */
31 {OFFSET(gpmc_a4), MODE(2)}, /* txd1 */
[all …]
/u-boot/arch/mips/lib/
A Dasm-offsets.c20 OFFSET(PT_R0, pt_regs, regs[0]); in output_ptreg_defines()
21 OFFSET(PT_R1, pt_regs, regs[1]); in output_ptreg_defines()
22 OFFSET(PT_R2, pt_regs, regs[2]); in output_ptreg_defines()
23 OFFSET(PT_R3, pt_regs, regs[3]); in output_ptreg_defines()
24 OFFSET(PT_R4, pt_regs, regs[4]); in output_ptreg_defines()
25 OFFSET(PT_R5, pt_regs, regs[5]); in output_ptreg_defines()
26 OFFSET(PT_R6, pt_regs, regs[6]); in output_ptreg_defines()
27 OFFSET(PT_R7, pt_regs, regs[7]); in output_ptreg_defines()
28 OFFSET(PT_R8, pt_regs, regs[8]); in output_ptreg_defines()
52 OFFSET(PT_LO, pt_regs, lo); in output_ptreg_defines()
[all …]
/u-boot/board/vscom/baltos/
A Dmux.c41 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
43 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
50 {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */
51 {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */
52 {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */
62 {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */
64 {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */
65 {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */
66 {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */
67 {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */
[all …]
A Dboard.c333 {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
338 {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
339 {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
340 {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
341 {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
/u-boot/board/bosch/guardian/
A Dmux.c19 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
30 {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLDOWN_EN)},
31 {OFFSET(mii1_txen), (MODE(7) | PULLDOWN_EN)},
32 {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)},
33 {OFFSET(mdio_clk), (MODE(7) | PULLUP_EN)},
35 {OFFSET(uart1_txd), (MODE(7) | PULLUDDIS)},
36 {OFFSET(mii1_crs), (MODE(7) | PULLDOWN_EN)},
37 {OFFSET(rmii1_refclk), (MODE(7) | PULLDOWN_EN)},
38 {OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},
64 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)},
[all …]
/u-boot/board/tcl/sl50/
A Dmux.c18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
30 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
77 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
79 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
85 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
87 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
94 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
96 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
97 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
98 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
[all …]
/u-boot/board/phytec/phycore_am335x_r2/
A Dmux.c18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
36 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
38 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
46 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
49 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
56 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
58 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
59 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
64 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
87 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
[all …]
/u-boot/board/isee/igep003x/
A Dmux.c24 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
50 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
52 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
53 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
59 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
60 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
62 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
63 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
64 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
65 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
[all …]
/u-boot/board/grinn/chiliboard/
A Dboard.c36 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
45 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
51 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
52 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
53 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
54 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
55 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
56 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
57 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
59 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
[all …]
/u-boot/board/eets/pdu001/
A Dmux.c19 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
20 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
25 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
26 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
32 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
37 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
38 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
44 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
50 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
55 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
[all …]
/u-boot/drivers/clk/starfive/
A Dclk-jh7110.c26 #define OFFSET(id) ((id) * 4) macro
257 OFFSET(JH7110_SYSCLK_CPU_ROOT), 1, in jh7110_syscrg_init()
274 OFFSET(JH7110_SYSCLK_BUS_ROOT), 1, in jh7110_syscrg_init()
291 OFFSET(JH7110_SYSCLK_AHB0))); in jh7110_syscrg_init()
295 OFFSET(JH7110_SYSCLK_AHB1))); in jh7110_syscrg_init()
303 OFFSET(JH7110_SYSCLK_APB0))); in jh7110_syscrg_init()
307 OFFSET(JH7110_SYSCLK_QSPI_AHB))); in jh7110_syscrg_init()
311 OFFSET(JH7110_SYSCLK_QSPI_APB))); in jh7110_syscrg_init()
375 OFFSET(JH7110_SYSCLK_GMAC1_RX), 1, in jh7110_syscrg_init()
449 OFFSET(JH7110_SYSCLK_I2C2_APB))); in jh7110_syscrg_init()
[all …]
/u-boot/arch/arm/mach-omap2/am33xx/
A Dchilisom.c30 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
32 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
38 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
39 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
40 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
41 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
48 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
49 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
50 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
51 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
[all …]
/u-boot/board/ti/ti816x/
A Devm.c66 { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
67 { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
68 { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
69 { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
70 { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
71 { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
72 { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
/u-boot/arch/arm/include/asm/arch-am33xx/
A Dmux.h36 #define OFFSET(x) (unsigned int) (&((struct pad_signals *)\ macro
/u-boot/include/linux/
A Dkbuild.h14 #define OFFSET(sym, str, mem) \ macro
/u-boot/drivers/thermal/
A Dimx_thermal.c29 #define OFFSET 3580661 macro
129 temperature = div_s64_rem(c2 - n_meas * c1 + OFFSET, 1000000, &rem); in read_cpu_temperature()

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