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Searched refs:OUTPUT_MIN_HZ (Results 1 – 10 of 10) sorted by relevance

/u-boot/drivers/clk/rockchip/
A Dclk_rk3036.c28 OUTPUT_MIN_HZ = 24 * 1000000, enumerator
64 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); in rkclk_set_pll()
A Dclk_rk322x.c29 OUTPUT_MIN_HZ = 24 * 1000000, enumerator
61 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); in rkclk_set_pll()
A Dclk_rk3128.c28 OUTPUT_MIN_HZ = 24 * 1000000, enumerator
56 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); in rkclk_set_pll()
A Dclk_rk3188.c51 OUTPUT_MIN_HZ = 30 * 1000000, enumerator
102 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && in rkclk_set_pll()
A Dclk_rk3066.c48 OUTPUT_MIN_HZ = 30 * 1000000, enumerator
97 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && in rk3066_clk_set_pll()
A Dclk_rv1108.c32 OUTPUT_MIN_HZ = 24 * 1000000, enumerator
85 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); in rkclk_set_pll()
A Dclk_rk3288.c51 OUTPUT_MIN_HZ = 27500000, enumerator
163 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && in rkclk_set_pll()
A Dclk_pll.c43 OUTPUT_MIN_HZ = 24 * 1000000, enumerator
A Dclk_px30.c31 OUTPUT_MIN_HZ = 24 * 1000000, enumerator
227 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); in rkclk_set_pll()
A Dclk_rk3308.c30 OUTPUT_MIN_HZ = 24 * 1000000, enumerator

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