Searched refs:PLL3 (Results 1 – 11 of 11) sorted by relevance
| /u-boot/arch/arm/mach-imx/imx8ulp/ |
| A D | cgc.c | 420 case PLL3: in decode_pll()
458 pll = PLL3; in cgc_pll_vcodiv_rate()
484 pll = PLL3; in cgc_pll_pfd_rate()
692 case PLL3: in cgc_clk_get_rate()
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| A D | clock.c | 536 printf("PLL3 %8d MHz\n", cgc_clk_get_rate(PLL3) / 1000000); in do_mx8ulp_showclocks()
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| /u-boot/include/dt-bindings/clock/ |
| A D | stm32mp13-clks.h | 21 #define PLL3 8 macro
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| A D | stm32mp1-clks.h | 185 #define PLL3 178 macro
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| /u-boot/arch/arm/include/asm/arch-imx8ulp/ |
| A D | cgc.h | 27 PLL3, enumerator
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| /u-boot/arch/arm/dts/ |
| A D | stm32mp15xx-dhcor-u-boot.dtsi | 153 * m ... for PLL1,2: m=2 ; for PLL3,4: m=1
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| A D | stm32mp15xx-dhcom-u-boot.dtsi | 199 * m ... for PLL1,2: m=2 ; for PLL3,4: m=1
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| /u-boot/doc/ |
| A D | README.Heterogeneous-SoCs | 55 PLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the
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| /u-boot/drivers/video/tegra124/ |
| A D | sor.c | 567 DUMP_REG(PLL3); in dump_sor_reg()
708 tegra_sor_write_field(sor, PLL3, in tegra_dc_sor_enable_dp()
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| A D | sor.h | 282 #define PLL3 0x1a macro
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | st,stm32mp1.txt | 26 MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
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