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Searched refs:PLLE_MISC (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-tegra/tegra20/
A Dclock.c678 #define PLLE_MISC 0x0ec macro
703 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_train()
731 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
735 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
737 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
746 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
750 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
762 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
/u-boot/arch/arm/mach-tegra/tegra30/
A Dclock.c740 #define PLLE_MISC 0x0ec macro
765 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_train()
793 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
797 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
799 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
825 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
829 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
841 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
/u-boot/arch/arm/mach-tegra/tegra210/
A Dclock.c1162 #define PLLE_MISC 0x0ec macro
1198 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
1200 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
1219 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
1224 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
1235 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
/u-boot/arch/arm/mach-tegra/tegra124/
A Dclock.c987 #define PLLE_MISC 0x0ec macro
1015 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
1022 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()

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