Searched refs:PLL_GPLL (Results 1 – 25 of 33) sorted by relevance
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| /u-boot/include/dt-bindings/clock/ |
| A D | rk3036-cru.h | 13 #define PLL_GPLL 3 macro
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| A D | rk3188-cru-common.h | 14 #define PLL_GPLL 4 macro
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| A D | rk3128-cru.h | 14 #define PLL_GPLL 4 macro
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| A D | rk3228-cru.h | 14 #define PLL_GPLL 4 macro
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| A D | rv1108-cru.h | 13 #define PLL_GPLL 2 macro
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| A D | px30-cru.h | 180 #define PLL_GPLL 1 macro
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| A D | rk3288-cru.h | 14 #define PLL_GPLL 4 macro
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| A D | rk3328-cru.h | 14 #define PLL_GPLL 4 macro
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| A D | rk3368-cru.h | 14 #define PLL_GPLL 5 macro
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| A D | rockchip,rv1126-cru.h | 13 #define PLL_GPLL 1 macro
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| A D | rk3399-cru.h | 14 #define PLL_GPLL 5 macro
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| A D | rockchip,rk3588-cru.h | 21 #define PLL_GPLL 6 macro
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| A D | rk3568-cru.h | 73 #define PLL_GPLL 4 macro
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| /u-boot/arch/arm/dts/ |
| A D | rk3566-anbernic-rgxx3-u-boot.dtsi | 23 <&cru PLL_GPLL>,
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| A D | rk3036.dtsi | 106 assigned-clocks = <&cru PLL_GPLL>;
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| A D | rk3128.dtsi | 238 assigned-clocks = <&cru PLL_GPLL>;
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| A D | rk3066a.dtsi | 210 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
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| A D | rk3399-gru.dtsi | 353 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rk3588.c | 62 [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3588_PLL_CON(112),
1486 case PLL_GPLL: in rk3588_clk_get_rate()
1647 case PLL_GPLL: in rk3588_clk_set_rate()
1805 else if (parent->id == PLL_GPLL) in rk3588_dclk_vop_set_parent()
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| A D | clk_rk322x.c | 398 case PLL_GPLL: in rk322x_clk_set_rate()
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| A D | clk_rv1126.c | 70 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126_PMU_PLL_CON(0),
382 case PLL_GPLL: in rv1126_pmuclk_get_rate()
422 case PLL_GPLL: in rv1126_pmuclk_set_rate()
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| A D | clk_rk3368.c | 467 case PLL_GPLL: in rk3368_clk_get_rate()
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| A D | clk_rk3066.c | 577 case PLL_GPLL: in rk3066_clk_set_rate()
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| A D | clk_px30.c | 1600 case PLL_GPLL: in px30_pmuclk_get_rate()
1620 case PLL_GPLL: in px30_pmuclk_set_rate()
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| A D | clk_rk3288.c | 882 case PLL_GPLL: in rk3288_clk_set_rate()
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Completed in 884 milliseconds
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