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Searched refs:PLL_VPLL (Results 1 – 8 of 8) sorted by relevance

/u-boot/arch/arm/dts/
A Drk3566-radxa-cm3-io.dts259 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
A Drk3568-evb.dts679 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
A Drk3566-anbernic-rgxx3.dtsi773 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
A Drk3568-rock-3a.dts845 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
A Drk3399.dtsi1805 <&cru PLL_VPLL>,
/u-boot/include/dt-bindings/clock/
A Drk3399-cru.h16 #define PLL_VPLL 7 macro
A Drk3568-cru.h74 #define PLL_VPLL 5 macro
/u-boot/drivers/clk/rockchip/
A Dclk_rk3568.c88 [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3568_PLL_CON(40),
2353 case PLL_VPLL: in rk3568_clk_get_rate()
2533 case PLL_VPLL: in rk3568_clk_set_rate()
2781 if (parent->id == PLL_VPLL) { in rk3568_dclk_vop_set_parent()

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