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Searched refs:QIXIS_BASE_PHYS (Results 1 – 17 of 17) sorted by relevance

/u-boot/board/freescale/t208xqds/
A Dlaw.c21 #ifdef QIXIS_BASE_PHYS
22 SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
A Dtlb.c129 #ifdef QIXIS_BASE_PHYS
130 SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
/u-boot/include/configs/
A Dls1028ardb.h23 #define QIXIS_BASE_PHYS QIXIS_BASE macro
43 #define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
A Dls1028aqds.h19 #define QIXIS_BASE_PHYS QIXIS_BASE macro
39 #define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
A Dls2080a_common.h75 #define QIXIS_BASE_PHYS 0x20000000 macro
A Dls1088a_common.h84 #define QIXIS_BASE_PHYS 0x20000000 macro
A Dls1021aqds.h108 #define QIXIS_BASE_PHYS QIXIS_BASE macro
130 #define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
A Dls1043aqds.h122 #define QIXIS_BASE_PHYS QIXIS_BASE macro
142 #define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
A Dls1046aqds.h138 #define QIXIS_BASE_PHYS QIXIS_BASE macro
158 #define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
A DT208xQDS.h132 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) macro
135 #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
A Dls1088ardb.h111 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
A Dls2080ardb.h117 #define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
A Dls2080aqds.h123 #define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
A Dls1088aqds.h131 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
/u-boot/board/freescale/ls2080aqds/
A Dls2080aqds.c52 addr = QIXIS_BASE_PHYS; in get_qixis_addr()
/u-boot/board/freescale/ls2080ardb/
A Dls2080ardb.c98 addr = QIXIS_BASE_PHYS; in get_qixis_addr()
/u-boot/board/freescale/ls1088a/
A Dls1088a.c169 addr = QIXIS_BASE_PHYS; in get_qixis_addr()

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