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Searched refs:REG (Results 1 – 23 of 23) sorted by relevance

/u-boot/arch/arm/include/asm/arch-rockchip/
A Dgrf_rk3066.h12 #define REG(name, h, l) \ macro
82 REG(GPIO1B1, 2, 2), enumerator
86 REG(GPIO1B0, 0, 0), enumerator
101 REG(GPIO3B4, 8, 8), enumerator
105 REG(GPIO3B3, 6, 6), enumerator
109 REG(GPIO3B2, 4, 4), enumerator
113 REG(GPIO3B1, 2, 2), enumerator
117 REG(GPIO3B0, 0, 0), enumerator
198 REG(DTO_TE, 10, 9), enumerator
206 REG(DTO_OE, 2, 1), enumerator
[all …]
A Dcru_rk3066.h12 #define REG(name, h, l) \ macro
100 REG(MMC0_DIV, 5, 0), enumerator
109 REG(EMMC_DIV, 13, 8), enumerator
111 REG(SDIO_DIV, 5, 0), enumerator
121 REG(SPI1_DIV, 14, 8), enumerator
123 REG(SPI0_DIV, 6, 0), enumerator
135 REG(CPLL_MODE, 9, 8), enumerator
137 REG(DPLL_MODE, 5, 4), enumerator
147 REG(CLKR, 13, 8), enumerator
149 REG(CLKOD, 3, 0), enumerator
[all …]
/u-boot/drivers/i2c/
A Ddavinci_i2c.c34 REG(&(i2c_base->i2c_con)) = 0;\
81 REG(&(i2c_base->i2c_drr)); in _flush_rx()
97 REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll)); in _davinci_i2c_setspeed()
106 REG(&(i2c_base->i2c_con)) = 0; in _davinci_i2c_init()
113 REG(&(i2c_base->i2c_cnt)) = 0; in _davinci_i2c_init()
217 REG(&(i2c_base->i2c_cnt)) = 0; in _davinci_i2c_read()
218 REG(&(i2c_base->i2c_con)) = 0; in _davinci_i2c_read()
299 REG(&(i2c_base->i2c_cnt)) = 0; in _davinci_i2c_write()
300 REG(&(i2c_base->i2c_con)) = 0; in _davinci_i2c_write()
312 REG(&(i2c_base->i2c_con)) = 0; in _davinci_i2c_probe_chip()
[all …]
/u-boot/drivers/video/tidss/
A Dtidss_regs.h62 #define DSS_REVISION REG(DSS_REVISION)
63 #define DSS_SYSCONFIG REG(DSS_SYSCONFIG)
64 #define DSS_SYSSTATUS REG(DSS_SYSSTATUS)
65 #define DSS_IRQ_EOI REG(DSS_IRQ_EOI)
67 #define DSS_IRQSTATUS REG(DSS_IRQSTATUS)
74 #define WB_IRQENABLE REG(WB_IRQENABLE)
75 #define WB_IRQSTATUS REG(WB_IRQSTATUS)
80 #define DSS_CBA_CFG REG(DSS_CBA_CFG)
82 #define DSS_DBG_STATUS REG(DSS_DBG_STATUS)
96 #define DSS_MSS_VP1 REG(DSS_MSS_VP1)
[all …]
/u-boot/drivers/video/
A Dtda19988.c21 #define REG(page, addr) (((page) << 8) | (addr)) macro
29 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
37 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
38 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
57 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
58 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
96 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
101 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
102 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
103 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
[all …]
/u-boot/lib/dhry/
A Ddhry_2.c45 #ifndef REG
46 #define REG macro
120 REG One_Fifty Int_Index;
121 REG One_Fifty Int_Loc;
168 REG One_Thirty Int_Loc;
A Ddhry_1.c71 #ifndef REG
73 #define REG macro
99 void Proc_1 (REG Rec_Pointer Ptr_Val_Par);
116 REG One_Fifty Int_2_Loc; in dhry()
118 REG char Ch_Index; in dhry()
327 void Proc_1 (REG Rec_Pointer Ptr_Val_Par) in Proc_1()
330 REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; in Proc_1()
/u-boot/arch/arm/include/asm/arch-tegra/
A Dap.h20 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) argument
/u-boot/include/
A Dsym53c8xx.h222 #define REG(r) (r) macro
388 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
391 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
394 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
460 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
463 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
/u-boot/arch/arm/mach-tegra/
A Dpinmux-common.c98 #define MUX_REG(pin) REG(pin)
101 #define PULL_REG(pin) REG(pin)
104 #define TRI_REG(pin) REG(pin)
235 u32 *reg = REG(pin); in pinmux_set_io()
257 u32 *reg = REG(pin); in pinmux_set_lock()
284 u32 *reg = REG(pin); in pinmux_set_od()
309 u32 *reg = REG(pin); in pinmux_set_ioreset()
334 u32 *reg = REG(pin); in pinmux_set_rcv_sel()
359 u32 *reg = REG(pin); in pinmux_set_e_io_hv()
383 u32 *reg = REG(grp); in pinmux_set_schmt()
[all …]
A Dcpu.h31 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) argument
/u-boot/drivers/pinctrl/rockchip/
A Dpinctrl-rockchip.h442 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ argument
447 .route_offset = REG, \
452 #define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ argument
453 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT)
455 #define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ argument
456 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF)
458 #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ argument
459 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)
/u-boot/drivers/net/
A Dmcfmii.c30 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ argument
31 (REG & 0x1f) << 18))
32 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ argument
33 (REG & 0x1f) << 18) | (VAL & 0xffff))
A Dmpc8xx_fec.c678 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ argument
679 (REG & 0x1f) << 18))
681 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ argument
682 (REG & 0x1f) << 18) | \
/u-boot/board/davinci/da8xxevm/
A Dda850evm.c408 temp = REG(GPIO_BANK2_REG_SET_ADDR); in rmii_hw_init()
410 REG(GPIO_BANK2_REG_SET_ADDR) = temp; in rmii_hw_init()
413 temp = REG(GPIO_BANK2_REG_DIR_ADDR); in rmii_hw_init()
415 REG(GPIO_BANK2_REG_DIR_ADDR) = temp; in rmii_hw_init()
A Domapl138_lcdk.c257 if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10) in dspwake()
268 REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE; in dspwake()
271 REG(PSC0_MDCTL + (15 * 4)) |= 0x100; in dspwake()
/u-boot/arch/arm/mach-davinci/include/mach/
A Dhardware.h18 #define REG(addr) (*(volatile unsigned int *)(addr)) macro
394 unsigned int jtag_id = REG(JTAG_ID_REG); in cpu_is_da830()
401 unsigned int jtag_id = REG(JTAG_ID_REG); in cpu_is_da850()
409 return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ? in get_async3_src()
/u-boot/arch/arm/mach-keystone/include/mach/
A Dhardware.h19 #define REG(addr) (*(volatile unsigned int *)(addr)) macro
/u-boot/drivers/mmc/
A Ddavinci_mmc.c23 #define get_val(addr) REG(addr)
24 #define set_val(addr, val) REG(addr) = (val)
/u-boot/arch/arm/mach-davinci/
A Dda850_lowlevel.c25 REG(UART0_PWREMU_MGMT) = 0x00006001; in davinci_enable_uart0()
/u-boot/arch/arm/dts/
A Dam5729-beagleboneai.dts156 reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */
157 <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */
/u-boot/drivers/ram/k3-ddrss/
A Dk3-ddrss.c178 #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\ argument
179 char *i, *pstr = xstr(REG); offset = 0;\
/u-boot/doc/
A DREADME.armada-secureboot111 | | REG header(s) | |

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