1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef __DRIVERS_PINCTRL_ROCKCHIP_H 7 #define __DRIVERS_PINCTRL_ROCKCHIP_H 8 9 #include <linux/bitops.h> 10 #include <linux/types.h> 11 12 #define RK_GPIO0_A0 0 13 #define RK_GPIO0_A1 1 14 #define RK_GPIO0_A2 2 15 #define RK_GPIO0_A3 3 16 #define RK_GPIO0_A4 4 17 #define RK_GPIO0_A5 5 18 #define RK_GPIO0_A6 6 19 #define RK_GPIO0_A7 7 20 #define RK_GPIO0_B0 8 21 #define RK_GPIO0_B1 9 22 #define RK_GPIO0_B2 10 23 #define RK_GPIO0_B3 11 24 #define RK_GPIO0_B4 12 25 #define RK_GPIO0_B5 13 26 #define RK_GPIO0_B6 14 27 #define RK_GPIO0_B7 15 28 #define RK_GPIO0_C0 16 29 #define RK_GPIO0_C1 17 30 #define RK_GPIO0_C2 18 31 #define RK_GPIO0_C3 19 32 #define RK_GPIO0_C4 20 33 #define RK_GPIO0_C5 21 34 #define RK_GPIO0_C6 22 35 #define RK_GPIO0_C7 23 36 #define RK_GPIO0_D0 24 37 #define RK_GPIO0_D1 25 38 #define RK_GPIO0_D2 26 39 #define RK_GPIO0_D3 27 40 #define RK_GPIO0_D4 28 41 #define RK_GPIO0_D5 29 42 #define RK_GPIO0_D6 30 43 #define RK_GPIO0_D7 31 44 45 #define RK_GPIO1_A0 32 46 #define RK_GPIO1_A1 33 47 #define RK_GPIO1_A2 34 48 #define RK_GPIO1_A3 35 49 #define RK_GPIO1_A4 36 50 #define RK_GPIO1_A5 37 51 #define RK_GPIO1_A6 38 52 #define RK_GPIO1_A7 39 53 #define RK_GPIO1_B0 40 54 #define RK_GPIO1_B1 41 55 #define RK_GPIO1_B2 42 56 #define RK_GPIO1_B3 43 57 #define RK_GPIO1_B4 44 58 #define RK_GPIO1_B5 45 59 #define RK_GPIO1_B6 46 60 #define RK_GPIO1_B7 47 61 #define RK_GPIO1_C0 48 62 #define RK_GPIO1_C1 49 63 #define RK_GPIO1_C2 50 64 #define RK_GPIO1_C3 51 65 #define RK_GPIO1_C4 52 66 #define RK_GPIO1_C5 53 67 #define RK_GPIO1_C6 54 68 #define RK_GPIO1_C7 55 69 #define RK_GPIO1_D0 56 70 #define RK_GPIO1_D1 57 71 #define RK_GPIO1_D2 58 72 #define RK_GPIO1_D3 59 73 #define RK_GPIO1_D4 60 74 #define RK_GPIO1_D5 61 75 #define RK_GPIO1_D6 62 76 #define RK_GPIO1_D7 63 77 78 #define RK_GPIO2_A0 64 79 #define RK_GPIO2_A1 65 80 #define RK_GPIO2_A2 66 81 #define RK_GPIO2_A3 67 82 #define RK_GPIO2_A4 68 83 #define RK_GPIO2_A5 69 84 #define RK_GPIO2_A6 70 85 #define RK_GPIO2_A7 71 86 #define RK_GPIO2_B0 72 87 #define RK_GPIO2_B1 73 88 #define RK_GPIO2_B2 74 89 #define RK_GPIO2_B3 75 90 #define RK_GPIO2_B4 76 91 #define RK_GPIO2_B5 77 92 #define RK_GPIO2_B6 78 93 #define RK_GPIO2_B7 79 94 #define RK_GPIO2_C0 80 95 #define RK_GPIO2_C1 81 96 #define RK_GPIO2_C2 82 97 #define RK_GPIO2_C3 83 98 #define RK_GPIO2_C4 84 99 #define RK_GPIO2_C5 85 100 #define RK_GPIO2_C6 86 101 #define RK_GPIO2_C7 87 102 #define RK_GPIO2_D0 88 103 #define RK_GPIO2_D1 89 104 #define RK_GPIO2_D2 90 105 #define RK_GPIO2_D3 91 106 #define RK_GPIO2_D4 92 107 #define RK_GPIO2_D5 93 108 #define RK_GPIO2_D6 94 109 #define RK_GPIO2_D7 95 110 111 #define RK_GPIO3_A0 96 112 #define RK_GPIO3_A1 97 113 #define RK_GPIO3_A2 98 114 #define RK_GPIO3_A3 99 115 #define RK_GPIO3_A4 100 116 #define RK_GPIO3_A5 101 117 #define RK_GPIO3_A6 102 118 #define RK_GPIO3_A7 103 119 #define RK_GPIO3_B0 104 120 #define RK_GPIO3_B1 105 121 #define RK_GPIO3_B2 106 122 #define RK_GPIO3_B3 107 123 #define RK_GPIO3_B4 108 124 #define RK_GPIO3_B5 109 125 #define RK_GPIO3_B6 110 126 #define RK_GPIO3_B7 111 127 #define RK_GPIO3_C0 112 128 #define RK_GPIO3_C1 113 129 #define RK_GPIO3_C2 114 130 #define RK_GPIO3_C3 115 131 #define RK_GPIO3_C4 116 132 #define RK_GPIO3_C5 117 133 #define RK_GPIO3_C6 118 134 #define RK_GPIO3_C7 119 135 #define RK_GPIO3_D0 120 136 #define RK_GPIO3_D1 121 137 #define RK_GPIO3_D2 122 138 #define RK_GPIO3_D3 123 139 #define RK_GPIO3_D4 124 140 #define RK_GPIO3_D5 125 141 #define RK_GPIO3_D6 126 142 #define RK_GPIO3_D7 127 143 144 #define RK_GPIO4_A0 128 145 #define RK_GPIO4_A1 129 146 #define RK_GPIO4_A2 130 147 #define RK_GPIO4_A3 131 148 #define RK_GPIO4_A4 132 149 #define RK_GPIO4_A5 133 150 #define RK_GPIO4_A6 134 151 #define RK_GPIO4_A7 135 152 #define RK_GPIO4_B0 136 153 #define RK_GPIO4_B1 137 154 #define RK_GPIO4_B2 138 155 #define RK_GPIO4_B3 139 156 #define RK_GPIO4_B4 140 157 #define RK_GPIO4_B5 141 158 #define RK_GPIO4_B6 142 159 #define RK_GPIO4_B7 143 160 #define RK_GPIO4_C0 144 161 #define RK_GPIO4_C1 145 162 #define RK_GPIO4_C2 146 163 #define RK_GPIO4_C3 147 164 #define RK_GPIO4_C4 148 165 #define RK_GPIO4_C5 149 166 #define RK_GPIO4_C6 150 167 #define RK_GPIO4_C7 151 168 #define RK_GPIO4_D0 152 169 #define RK_GPIO4_D1 153 170 #define RK_GPIO4_D2 154 171 #define RK_GPIO4_D3 155 172 #define RK_GPIO4_D4 156 173 #define RK_GPIO4_D5 157 174 #define RK_GPIO4_D6 158 175 #define RK_GPIO4_D7 159 176 177 #define RK_GENMASK_VAL(h, l, v) \ 178 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 179 180 /** 181 * Encode variants of iomux registers into a type variable 182 */ 183 #define IOMUX_GPIO_ONLY BIT(0) 184 #define IOMUX_WIDTH_4BIT BIT(1) 185 #define IOMUX_SOURCE_PMU BIT(2) 186 #define IOMUX_UNROUTED BIT(3) 187 #define IOMUX_WIDTH_3BIT BIT(4) 188 #define IOMUX_8WIDTH_2BIT BIT(5) 189 #define IOMUX_L_SOURCE_PMU BIT(6) 190 191 /** 192 * Defined some common pins constants 193 */ 194 #define ROCKCHIP_PULL_BITS_PER_PIN 2 195 #define ROCKCHIP_PULL_PINS_PER_REG 8 196 #define ROCKCHIP_PULL_BANK_STRIDE 16 197 #define ROCKCHIP_DRV_BITS_PER_PIN 2 198 #define ROCKCHIP_DRV_PINS_PER_REG 8 199 #define ROCKCHIP_DRV_BANK_STRIDE 16 200 #define ROCKCHIP_DRV_3BITS_PER_PIN 3 201 202 /** 203 * @type: iomux variant using IOMUX_* constants 204 * @offset: if initialized to -1 it will be autocalculated, by specifying 205 * an initial offset value the relevant source offset can be reset 206 * to a new value for autocalculating the following iomux registers. 207 */ 208 struct rockchip_iomux { 209 int type; 210 int offset; 211 }; 212 213 /** 214 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 215 */ 216 enum rockchip_pin_drv_type { 217 DRV_TYPE_IO_DEFAULT = 0, 218 DRV_TYPE_IO_1V8_OR_3V0, 219 DRV_TYPE_IO_1V8_ONLY, 220 DRV_TYPE_IO_1V8_3V0_AUTO, 221 DRV_TYPE_IO_3V3_ONLY, 222 DRV_TYPE_MAX 223 }; 224 225 /** 226 * enum type index corresponding to rockchip_pull_list arrays index. 227 */ 228 enum rockchip_pin_pull_type { 229 PULL_TYPE_IO_DEFAULT = 0, 230 PULL_TYPE_IO_1V8_ONLY, 231 PULL_TYPE_MAX 232 }; 233 234 /** 235 * Rockchip pinctrl route type 236 * 237 * DEFAULT : Same regmap as pin iomux 238 * TOPGRF : Mux route setting in topgrf 239 * PMUGRF : Mux route setting in pmugrf 240 * INVALID : Nnot need to set mux route 241 */ 242 enum rockchip_pin_route_type { 243 ROUTE_TYPE_DEFAULT = 0, 244 ROUTE_TYPE_TOPGRF = 1, 245 ROUTE_TYPE_PMUGRF = 2, 246 247 ROUTE_TYPE_INVALID = -1, 248 }; 249 250 /** 251 * @drv_type: drive strength variant using rockchip_perpin_drv_type 252 * @offset: if initialized to -1 it will be autocalculated, by specifying 253 * an initial offset value the relevant source offset can be reset 254 * to a new value for autocalculating the following drive strength 255 * registers. if used chips own cal_drv func instead to calculate 256 * registers offset, the variant could be ignored. 257 */ 258 struct rockchip_drv { 259 enum rockchip_pin_drv_type drv_type; 260 int offset; 261 }; 262 263 /** 264 * @priv: common pinctrl private basedata 265 * @pin_base: first pin number 266 * @nr_pins: number of pins in this bank 267 * @name: name of the bank 268 * @bank_num: number of the bank, to account for holes 269 * @iomux: array describing the 4 iomux sources of the bank 270 * @drv: array describing the 4 drive strength sources of the bank 271 * @pull_type: array describing the 4 pull type sources of the bank 272 * @recalced_mask: bits describing the mux recalced pins of per bank 273 * @route_mask: bits describing the routing pins of per bank 274 */ 275 struct rockchip_pin_bank { 276 struct rockchip_pinctrl_priv *priv; 277 u32 pin_base; 278 u8 nr_pins; 279 char *name; 280 u8 bank_num; 281 struct rockchip_iomux iomux[4]; 282 struct rockchip_drv drv[4]; 283 enum rockchip_pin_pull_type pull_type[4]; 284 u32 recalced_mask; 285 u32 route_mask; 286 }; 287 288 #define PIN_BANK(id, pins, label) \ 289 { \ 290 .bank_num = id, \ 291 .nr_pins = pins, \ 292 .name = label, \ 293 .iomux = { \ 294 { .offset = -1 }, \ 295 { .offset = -1 }, \ 296 { .offset = -1 }, \ 297 { .offset = -1 }, \ 298 }, \ 299 } 300 301 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 302 { \ 303 .bank_num = id, \ 304 .nr_pins = pins, \ 305 .name = label, \ 306 .iomux = { \ 307 { .type = iom0, .offset = -1 }, \ 308 { .type = iom1, .offset = -1 }, \ 309 { .type = iom2, .offset = -1 }, \ 310 { .type = iom3, .offset = -1 }, \ 311 }, \ 312 } 313 314 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ 315 iom3, offset0, offset1, offset2, \ 316 offset3) \ 317 { \ 318 .bank_num = id, \ 319 .nr_pins = pins, \ 320 .name = label, \ 321 .iomux = { \ 322 { .type = iom0, .offset = offset0 }, \ 323 { .type = iom1, .offset = offset1 }, \ 324 { .type = iom2, .offset = offset2 }, \ 325 { .type = iom3, .offset = offset3 }, \ 326 }, \ 327 } 328 329 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 330 { \ 331 .bank_num = id, \ 332 .nr_pins = pins, \ 333 .name = label, \ 334 .iomux = { \ 335 { .offset = -1 }, \ 336 { .offset = -1 }, \ 337 { .offset = -1 }, \ 338 { .offset = -1 }, \ 339 }, \ 340 .drv = { \ 341 { .drv_type = type0, .offset = -1 }, \ 342 { .drv_type = type1, .offset = -1 }, \ 343 { .drv_type = type2, .offset = -1 }, \ 344 { .drv_type = type3, .offset = -1 }, \ 345 }, \ 346 } 347 348 #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \ 349 iom2, iom3, pull0, pull1, \ 350 pull2, pull3) \ 351 { \ 352 .bank_num = id, \ 353 .nr_pins = pins, \ 354 .name = label, \ 355 .iomux = { \ 356 { .type = iom0, .offset = -1 }, \ 357 { .type = iom1, .offset = -1 }, \ 358 { .type = iom2, .offset = -1 }, \ 359 { .type = iom3, .offset = -1 }, \ 360 }, \ 361 .pull_type[0] = pull0, \ 362 .pull_type[1] = pull1, \ 363 .pull_type[2] = pull2, \ 364 .pull_type[3] = pull3, \ 365 } 366 367 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 368 drv2, drv3, pull0, pull1, \ 369 pull2, pull3) \ 370 { \ 371 .bank_num = id, \ 372 .nr_pins = pins, \ 373 .name = label, \ 374 .iomux = { \ 375 { .offset = -1 }, \ 376 { .offset = -1 }, \ 377 { .offset = -1 }, \ 378 { .offset = -1 }, \ 379 }, \ 380 .drv = { \ 381 { .drv_type = drv0, .offset = -1 }, \ 382 { .drv_type = drv1, .offset = -1 }, \ 383 { .drv_type = drv2, .offset = -1 }, \ 384 { .drv_type = drv3, .offset = -1 }, \ 385 }, \ 386 .pull_type[0] = pull0, \ 387 .pull_type[1] = pull1, \ 388 .pull_type[2] = pull2, \ 389 .pull_type[3] = pull3, \ 390 } 391 392 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 393 iom2, iom3, drv0, drv1, drv2, \ 394 drv3, offset0, offset1, \ 395 offset2, offset3) \ 396 { \ 397 .bank_num = id, \ 398 .nr_pins = pins, \ 399 .name = label, \ 400 .iomux = { \ 401 { .type = iom0, .offset = -1 }, \ 402 { .type = iom1, .offset = -1 }, \ 403 { .type = iom2, .offset = -1 }, \ 404 { .type = iom3, .offset = -1 }, \ 405 }, \ 406 .drv = { \ 407 { .drv_type = drv0, .offset = offset0 }, \ 408 { .drv_type = drv1, .offset = offset1 }, \ 409 { .drv_type = drv2, .offset = offset2 }, \ 410 { .drv_type = drv3, .offset = offset3 }, \ 411 }, \ 412 } 413 414 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 415 label, iom0, iom1, iom2, \ 416 iom3, drv0, drv1, drv2, \ 417 drv3, offset0, offset1, \ 418 offset2, offset3, pull0, \ 419 pull1, pull2, pull3) \ 420 { \ 421 .bank_num = id, \ 422 .nr_pins = pins, \ 423 .name = label, \ 424 .iomux = { \ 425 { .type = iom0, .offset = -1 }, \ 426 { .type = iom1, .offset = -1 }, \ 427 { .type = iom2, .offset = -1 }, \ 428 { .type = iom3, .offset = -1 }, \ 429 }, \ 430 .drv = { \ 431 { .drv_type = drv0, .offset = offset0 }, \ 432 { .drv_type = drv1, .offset = offset1 }, \ 433 { .drv_type = drv2, .offset = offset2 }, \ 434 { .drv_type = drv3, .offset = offset3 }, \ 435 }, \ 436 .pull_type[0] = pull0, \ 437 .pull_type[1] = pull1, \ 438 .pull_type[2] = pull2, \ 439 .pull_type[3] = pull3, \ 440 } 441 442 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 443 { \ 444 .bank_num = ID, \ 445 .pin = PIN, \ 446 .func = FUNC, \ 447 .route_offset = REG, \ 448 .route_val = VAL, \ 449 .route_type = FLAG, \ 450 } 451 452 #define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ 453 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT) 454 455 #define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ 456 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF) 457 458 #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ 459 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF) 460 461 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ 462 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P) 463 464 /** 465 * struct rockchip_mux_recalced_data: recalculate a pin iomux data. 466 * @num: bank number. 467 * @pin: pin number. 468 * @reg: register offset. 469 * @bit: index at register. 470 * @mask: mask bit 471 */ 472 struct rockchip_mux_recalced_data { 473 u8 num; 474 u8 pin; 475 u32 reg; 476 u8 bit; 477 u8 mask; 478 }; 479 480 /** 481 * struct rockchip_mux_route_data: route a pin iomux data. 482 * @bank_num: bank number. 483 * @pin: index at register or used to calc index. 484 * @func: the min pin. 485 * @route_type: the register type. 486 * @route_offset: the max pin. 487 * @route_val: the register offset. 488 */ 489 struct rockchip_mux_route_data { 490 u8 bank_num; 491 u8 pin; 492 u8 func; 493 enum rockchip_pin_route_type route_type : 8; 494 u32 route_offset; 495 u32 route_val; 496 }; 497 498 /** 499 */ 500 struct rockchip_pin_ctrl { 501 struct rockchip_pin_bank *pin_banks; 502 u32 nr_banks; 503 u32 nr_pins; 504 int grf_mux_offset; 505 int pmu_mux_offset; 506 int grf_drv_offset; 507 int pmu_drv_offset; 508 struct rockchip_mux_recalced_data *iomux_recalced; 509 u32 niomux_recalced; 510 struct rockchip_mux_route_data *iomux_routes; 511 u32 niomux_routes; 512 513 int (*set_mux)(struct rockchip_pin_bank *bank, 514 int pin, int mux); 515 int (*set_pull)(struct rockchip_pin_bank *bank, 516 int pin_num, int pull); 517 int (*set_drive)(struct rockchip_pin_bank *bank, 518 int pin_num, int strength); 519 int (*set_schmitt)(struct rockchip_pin_bank *bank, 520 int pin_num, int enable); 521 }; 522 523 /** 524 */ 525 struct rockchip_pinctrl_priv { 526 struct rockchip_pin_ctrl *ctrl; 527 struct regmap *regmap_base; 528 struct regmap *regmap_pmu; 529 }; 530 531 extern const struct pinctrl_ops rockchip_pinctrl_ops; 532 int rockchip_pinctrl_probe(struct udevice *dev); 533 void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 534 int *reg, u8 *bit, int *mask); 535 int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask); 536 int rockchip_translate_drive_value(int type, int strength); 537 int rockchip_translate_pull_value(int type, int pull); 538 539 #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */ 540