Searched refs:RL (Results 1 – 10 of 10) sorted by relevance
| /u-boot/drivers/ddr/microchip/ |
| A D | ddr2.c | 38 writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) | in ddr2_phy_init()
168 ((RL - WL + 3) << 28)), &ctrl->dlycfg0); in ddr2_ctrl_init()
177 (((RL + 5) >> 4) << 29) | in ddr2_ctrl_init()
186 ((RL + 3) << 28)), &ctrl->dlycfg2); in ddr2_ctrl_init()
196 writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3), in ddr2_ctrl_init()
228 host_load_cmd(ctrl, 5, temp, LOAD_MODE_CMD | (RL << 28) | (2 << 24), in ddr2_ctrl_init()
241 host_load_cmd(ctrl, 9, temp, LOAD_MODE_CMD | (RL << 28) | (3 << 24), in ddr2_ctrl_init()
|
| A D | ddr2_timing.h | 17 #define RL 5 macro
|
| /u-boot/arch/arm/mach-omap2/omap4/ |
| A D | emif.c | 25 .RL = 6,
49 .RL = 3,
|
| A D | sdram_elpida.c | 193 .RL = 6,
216 .RL = 5,
239 .RL = 3,
|
| /u-boot/arch/arm/mach-omap2/omap5/ |
| A D | emif.c | 27 .RL = 8,
|
| A D | sdram.c | 615 .RL = 8,
|
| /u-boot/arch/arm/mach-omap2/ |
| A D | emif-common.c | 657 u8 RL) in get_sdram_config_reg() argument
667 config_reg |= RL << EMIF_REG_CL_SHIFT; in get_sdram_config_reg()
856 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) in get_ddr_phy_ctrl_1() argument
860 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT; in get_ddr_phy_ctrl_1()
|
| /u-boot/arch/arm/include/asm/arch-mx5/ |
| A D | imx-regs.h | 180 #define RL(x) (((x) & 0x3) << 8) macro
|
| /u-boot/arch/arm/include/asm/ |
| A D | emif.h | 1140 u8 RL; member
|
| /u-boot/arch/arm/mach-mvebu/ |
| A D | Kconfig | 236 failure, RL, WL errors and other algorithm failure. At level 1,
|
Completed in 30 milliseconds