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Searched refs:SRDS1_MAX_LANES (Results 1 – 9 of 9) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc85xx/
A Dp1023_serdes.c14 #define SRDS1_MAX_LANES 4 macro
18 static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
53 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
A Dc29x_serdes.c13 #define SRDS1_MAX_LANES 4 macro
19 u8 lanes[SRDS1_MAX_LANES];
64 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
A Dmpc8548_serdes.c13 #define SRDS1_MAX_LANES 8 macro
17 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
51 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
A Dp2020_serdes.c13 #define SRDS1_MAX_LANES 4 macro
17 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
59 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
A Dp1010_serdes.c14 #define SRDS1_MAX_LANES 4 macro
19 static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
70 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
A Dp1021_serdes.c32 #define SRDS1_MAX_LANES 4 macro
36 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
72 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
A Dmpc8544_serdes.c13 #define SRDS1_MAX_LANES 8 macro
18 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
71 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
A Dbsc9132_serdes.c14 #define SRDS1_MAX_LANES 4 macro
18 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
95 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
A Dmpc8536_serdes.c53 #define SRDS1_MAX_LANES 8 macro
58 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
231 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()

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