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Searched refs:SRDS_MAX_LANES (Results 1 – 25 of 27) sorted by relevance

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/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dls1088a_serdes.c13 u8 lanes[SRDS_MAX_LANES];
14 u8 rcw_lanes[SRDS_MAX_LANES];
67 int is_found, max_lane = SRDS_MAX_LANES; in serdes_get_number()
138 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dls1028a_serdes.c11 u8 lanes[SRDS_MAX_LANES];
12 u8 rcw_lanes[SRDS_MAX_LANES];
84 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dls1012a_serdes.c12 u8 lanes[SRDS_MAX_LANES];
67 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dls1043a_serdes.c12 u8 lanes[SRDS_MAX_LANES];
79 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dls1046a_serdes.c13 u8 lanes[SRDS_MAX_LANES];
94 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dls2080a_serdes.c11 u8 lanes[SRDS_MAX_LANES];
117 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dfsl_lsch3_serdes.c126 for (i = 0; i < SRDS_MAX_LANES; i++) { in serdes_get_first_lane()
159 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in serdes_init()
633 for (int i = 0; i < SRDS_MAX_LANES; i++) { in serdes_set_env()
638 tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE; in serdes_set_env()
A Dlx2160a_serdes.c11 u8 lanes[SRDS_MAX_LANES];
143 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dfsl_lsch2_serdes.c69 for (i = 0; i < SRDS_MAX_LANES; i++) { in serdes_get_first_lane()
120 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in serdes_init()
/u-boot/arch/arm/cpu/armv7/ls102xa/
A Dls102xa_serdes.c10 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
34 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dfsl_ls1_serdes.c67 for (i = 0; i < SRDS_MAX_LANES; i++) { in serdes_get_first_lane()
89 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in serdes_init()
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
A Dconfig.h26 #define SRDS_MAX_LANES 8 macro
99 #define SRDS_MAX_LANES 4 macro
135 #define SRDS_MAX_LANES 8 macro
177 #define SRDS_MAX_LANES 4 macro
/u-boot/arch/powerpc/cpu/mpc85xx/
A Dt1024_serdes.c12 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
47 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dt1040_serdes.c12 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
61 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dfsl_corenet_serdes.c67 } lanes[SRDS_MAX_LANES] = {
152 for (i = 0; i < SRDS_MAX_LANES; i++) { in __serdes_get_first_lane()
207 for (lane = first; lane < SRDS_MAX_LANES; lane++) { in __serdes_get_lane_count()
575 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in fsl_serdes_init()
672 for (lane = 0; lane < SRDS_MAX_LANES; lane++) in fsl_serdes_init()
690 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in fsl_serdes_init()
A Dp2041_serdes.c12 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
83 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dp4080_serdes.c13 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
75 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dp5040_serdes.c19 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
94 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dt2080_serdes.c15 u8 lanes[SRDS_MAX_LANES];
218 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dfsl_corenet2_serdes.c162 for (i = 0; i < SRDS_MAX_LANES; i++) { in serdes_get_first_lane()
337 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in serdes_init()
A Dp3041_serdes.c12 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
128 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dcmd_errata.c90 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in check_erratum_a4580()
A Db4860_serdes.c14 u8 lanes[SRDS_MAX_LANES];
279 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
A Dt4240_serdes.c14 u8 lanes[SRDS_MAX_LANES];
309 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
/u-boot/arch/arm/include/asm/arch-ls102xa/
A Dimmap_ls102xa.h295 #define SRDS_MAX_LANES 4 macro

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