Searched refs:STM32_DDRPHYC_BASE (Results 1 – 2 of 2) sorted by relevance
490 clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, in ddr_sw_self_refresh_in()494 clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, in ddr_sw_self_refresh_in()498 clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, in ddr_sw_self_refresh_in()505 setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD); in ddr_sw_self_refresh_in()509 clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, in ddr_sw_self_refresh_in()515 clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, in ddr_sw_self_refresh_in()523 clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE); in ddr_sw_self_refresh_in()598 clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, in ddr_sw_self_refresh_exit()624 STM32_DDRPHYC_BASE + DDRPHYC_PIR); in ddr_sw_self_refresh_exit()630 ret = secure_waitbits(STM32_DDRPHYC_BASE + DDRPHYC_PGSR, in ddr_sw_self_refresh_exit()[all …]
25 #define STM32_DDRPHYC_BASE 0x5A004000 macro
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