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Searched refs:STM32_DDR_BASE (Results 1 – 9 of 9) sorted by relevance

/u-boot/arch/arm/mach-stm32mp/
A Dspl.c136 const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1); in stm32_init_tzc_for_optee()
152 .base = STM32_DDR_BASE, in stm32_init_tzc_for_optee()
239 mmu_set_region_dcache_behaviour(STM32_DDR_BASE, in board_init_f()
A Dboot_params.c27 if (nt_fw_dtb >= STM32_DDR_BASE) { in board_fdt_blob_setup()
A DKconfig94 before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
A Dcpu.c68 start = STM32_DDR_BASE; in dram_bank_mmu_setup()
/u-boot/include/configs/
A Dstm32mp13_common.h16 #define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
A Dstm32mp15_common.h16 #define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
/u-boot/arch/arm/mach-stm32mp/include/mach/
A Dstm32.h55 #define STM32_DDR_BASE 0xC0000000 macro
/u-boot/drivers/ram/stm32mp1/
A Dstm32mp1_tests.c51 *bufsize = get_ram_size((long *)STM32_DDR_BASE, in get_bufsize()
89 if (value < STM32_DDR_BASE) { in get_addr()
100 *addr = STM32_DDR_BASE; in get_addr()
1284 addr = (u32 *)(STM32_DDR_BASE + in test_read()
1333 addr = (u32 *)(STM32_DDR_BASE + in test_write()
A Dstm32mp1_ram.c371 priv->info.base = STM32_DDR_BASE; in stm32mp1_ddr_probe()

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