| /u-boot/drivers/clk/renesas/ |
| A D | rcar-gen3-cpg.h | 57 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
58 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
60 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
61 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
80 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
81 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
91 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
92 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
94 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
95 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
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| A D | renesas-cpg-mssr.h | 88 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
89 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
90 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
91 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
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| A D | r8a779a0-cpg-mssr.c | 55 #define DEF_PLL(_name, _id, _offset) \ argument
57 .offset = _offset)
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| /u-boot/arch/arm/cpu/armv7/bcm281xx/ |
| A D | clk-core.h | 177 .offset = (_offset), \
189 .offset = (_offset), \
200 .offset = (_offset), \
211 .offset = (_offset), \
221 .offset = (_offset), \
299 #define DIVIDER(_offset, _shift, _width) \ argument
301 .offset = (_offset), \
311 .offset = (_offset), \
352 .offset = (_offset), \
383 #define TRIGGER(_offset, _bit) \ argument
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| /u-boot/arch/arm/cpu/armv7/bcm235xx/ |
| A D | clk-core.h | 177 .offset = (_offset), \
189 .offset = (_offset), \
200 .offset = (_offset), \
211 .offset = (_offset), \
221 .offset = (_offset), \
299 #define DIVIDER(_offset, _shift, _width) \ argument
301 .offset = (_offset), \
311 .offset = (_offset), \
352 .offset = (_offset), \
383 #define TRIGGER(_offset, _bit) \ argument
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| /u-boot/include/fsl-mc/ |
| A D | fsl_mc_cmd.h | 80 #define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \ argument
81 ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg)))
83 #define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ argument
84 (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width)))
86 #define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ argument
87 ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
89 #define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ argument
90 (_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width)))
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| /u-boot/drivers/usb/musb-new/ |
| A D | musb_regs.h | 268 #define MUSB_INDEXED_OFFSET(_epnum, _offset) \ argument
269 (0x10 + (_offset))
272 #define MUSB_FLAT_OFFSET(_epnum, _offset) \ argument
273 (0x100 + (0x10*(_epnum)) + (_offset))
278 #define MUSB_TUSB_OFFSET(_epnum, _offset) \ argument
279 (0x10 + _offset)
294 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \ argument
295 (0x80 + (8*(_epnum)) + (_offset))
358 #define MUSB_INDEXED_OFFSET(_epnum, _offset) (_offset) argument
372 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) (_offset) argument
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| /u-boot/tools/dtoc/ |
| A D | fdt.py | 118 self._offset = offset
130 self._offset = poffset
284 self._offset = offset
318 return self._offset
350 if self._offset != my_offset:
351 self._offset = my_offset
352 name = fdt_obj.get_name(self._offset)
359 if subnode._offset is None:
585 if self._offset is None:
597 self._offset = offset
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| A D | test_fdt.py | 297 wrong_offset = self.dtb.GetNode('/i2c@0')._offset
298 self.node._offset = wrong_offset
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| A D | test_fdt | 297 wrong_offset = self.dtb.GetNode('/i2c@0')._offset
298 self.node._offset = wrong_offset
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| /u-boot/arch/arm/mach-socfpga/include/mach/ |
| A D | reset_manager.h | 28 #define RSTMGR_DEFINE(_bank, _offset) \ argument
29 ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
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| /u-boot/include/dm/ |
| A D | device.h | 273 #define dev_set_dma_offset(_dev, _offset) _dev->dma_offset = _offset argument
276 #define dev_set_dma_offset(_dev, _offset) argument
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| /u-boot/drivers/clk/stm32/ |
| A D | clk-stm32mp13.c | 175 #define MUX_CFG(id, src, _offset, _shift, _witdh) \ argument
179 .reg_off = (_offset), \
344 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \ argument
346 .reg_off = (_offset), \
484 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table) \ argument
486 .reg_off = _offset, \
564 #define SECF(_sec_id, _offset, _bit_idx) \ argument
566 .offset = _offset, \
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| /u-boot/arch/arm/mach-tegra/tegra124/ |
| A D | xusb-padctl.c | 85 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ argument
88 .offset = _offset, \
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| /u-boot/arch/arm/mach-tegra/tegra210/ |
| A D | xusb-padctl.c | 65 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ argument
68 .offset = _offset, \
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